Freescale Semiconductor MPC5565, Reference Manual

Page: 605 / 1153

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
16-28 Freescale Semiconductor
16.4.4.2 Clock Prescaler (CP)
A unified channel has a clock prescaler (CP) that divides the global clock prescaler (refer to Section 16.4.3,
“Global Clock Prescaler Submodule (GCP) ”) output signal to generate a clock enable for the internal
counter of the unified channel. It is a programmable 2-bit down counter. The global clock prescaler
submodule (GCP) output signal is prescaled by the value defined in
Table 16-9 according to the
UCPRE[0:1] bits in the EMIOS_CCR n . The output is clocked every time the counter reaches zero.
Counting is enabled by setting the UCPREN bit in the EMIOS_CCR n . The counter can be stopped at any
time by clearing this bit, thereby stopping the internal counter in the unified channel.
16.4.4.3 Effect of Freeze on a Unified Channel
When in debug mode and the EMIOS_MCR[FRZ] bit and the EMIOS_CCR n [FREN] bit are both set, the
internal counter and the unified channel’s capture and compare functions are halted. The UC is frozen in
its current state.
During freeze, all registers are accessible. When the unified channel is operating in an output mode, the
force match functions remain available, allowing the software to force the output to the desired level.
For input modes, any input events that occurs while the channel is frozen are ignored.
When exiting debug mode or freeze enable bit is cleared (FRZ in the EMIOS_MCR or FREN in the
EMIOS_CCR
n ) the channel actions resume.
16.4.4.4 Unified Channels Operating Modes
The mode of operation of a unified channel is determined by the mode select bits MODE[0:6] in the
EMIOS_CCR
n . See Table 16-10 for details.
When entering an output mode (except for GPIO mode), the output flip-flop is set to the complement of
the EDPOL bit in the EMIOS_CCR
n .
Because the internal counter EMIOS_CCNTR n continues to run in all modes (except for GPIO mode), it
is possible to use this counter as the UC time base unless it (the internal counter) is a required resource in
the operation of the selected mode.
To provide smooth waveform generation while allowing A and B registers to be asynchronously updated
during UC operation, the double-buffered modes MCB, OPWFMB, OPWMB, and OPWMCB are
provided (beginning at
Section 16.4.4.4.15, “Modulus Counter Buffered Mode (MCB) ”). In these modes
the A and B registers are double buffered. Descriptions of the double-buffered modes are presented
separately, because there are several basic differences from the single-buffered MC, OPWFM, OPWM,
and OPWMC modes.
In the following pages, Section 16.4.4.4.1, “General Purpose Input/Output Mode (GPIO) ” through
Section 16.4.4.4.14, “Output Pulse-Width Modulation Mode (OPWM) and Section 16.4.4.4.18, “Output
Pulse-Width Modulation, Buffered Mode (OPWMB) ” explain in detail the unified channels’ modes of
operation.