External Bus Interface (EBI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
12-8
Freescale Semiconductor
12.2.1
Detailed Signal Descriptions
Refer to
Chapter 2, “Signal Description
,” as not all signals are implemented in all device packages.
Refer to
for a description of the differences between the device design and the 324 package
limitations.
12.2.1.1
Address Lines: ADDR[8:31]
The ADDR[8:31] signals specify the physical address of the bus transaction. Refer to
on address bus configuration. The 24 address lines are bits 8 through 31 of the EBI’s 32-bit internal address
bus. Bits 0 through 7 are internally driven by the EBI for externally initiated accesses depending on the
internal slave accessed.
Refer to
Section 12.4.2.10.1, “Address Decoding for External Master Accesses
ADDR[8:31] is driven by the EBI or an external master depending on the module that controls the external
bus.
During a calibration bus access, ADDR[
n
]
reflects the same values as the CAL_ADDR[
n
] signals.
12.2.1.2
Data Lines: DATA[0:31]
DATA[0:31] is driven by the EBI when it owns the external bus and it initiates a write transaction to an
external device. The EBI also drives DATA[0:31] when an external master owns the external bus and
initiates a read transaction to an internal module.
DATA[0:31] is driven by an external device during a read transaction from the EBI. An external master
drives DATA[0:31] when it owns the bus and initiates a write transaction to an internal module or shared
external memory. For 8-bit and 16-bit transactions, the unused byte lanes do not supply valid data.
In the 324 BGA package, DATA[0:15] are used to transfer data.
During a calibration bus access, the DATA bus is not driven by the EBI.
12.2.1.3
Burst Data in Progress (BDIP)
BDIP is asserted by a master requesting the next data beat to follow the current data beat.
4
ADDR[8:11] signals are muxed as alternate signals with the chip select CS[0:3] and GPIO[0:3] signals.
ADDR[8:11] are also available as primary signals in the device design muxed with GPIO[4:7], however
ADDR[8:11]_GPIO[4:7] are not available in 324 package. Refer to
for more information.
5
The 324 package does not have balls for the calibration bus signals; only the VertiCal assembly currently
supports the calibration bus for this device.
6
CAL_ADDR[10:11] are separate signals from the EBI block, and are muxed onto CAL_CS[2:3] pins on MCU.
7
The CLKOUT signal is driven by the FMPLL Module.
Summary of Contents for MPC5565
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Page 34: ...MPC5565 Reference Manual Rev 1 0 Freescale Semiconductor 15...
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Page 553: ...Flash Memory MPC5565 Microcontroller Reference Manual Rev 1 0 13 38 Freescale Semiconductor...
Page 559: ...SRAM MPC5565 Microcontroller Reference Manual Rev 1 0 14 6 Freescale Semiconductor...
Page 973: ...Preface MPC5565 Microcontroller Reference Manual Rev 1 0 21 36 Freescale Semiconductor...
Page 1153: ...Calibration MPC5565 Microcontroller Reference Manual Rev 1 0 B 8 Freescale Semiconductor...
