Freescale Semiconductor MPC5565, Reference Manual

Page: 449 / 1153

External Bus Interface (EBI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
12-4 Freescale Semiconductor
12.1.3 Features
The device includes design for the following features:
• 1.8–3.3 V I/O
• Address bus is 32-bit with transfer size indication
• 32-bit internal address bus with transfer size indication
Table 12-2 shows the address bus packages supported:
Table 12-3 shows the data bus packages supported:
• 32-bit data bus available for both external memory accesses and transactions involving an external
master.
• Support for external master accesses to internal addresses
• Memory controller with support for various memory types:
— Synchronous burst SDR flash and SRAM
— Asynchronous/legacy flash and SRAM
• Burst support (wrapped only)
Table 12-2. Address Bus Sizes in MPC5565
324 BGA
EBI Address Bus Size
24 bits
1
1
24 bits available: ADDR[12:31] is the default pin set, then
CS[0:3]_ADDR[8:11]_GPIO [0:3] must be configured by PCR to ADDR[8:11] to
attain the 24-bit size.
20 bits
2
2
20 bits is the default EBI size for the 324 package (ADDR[12:31]).
Calibration Address Bus Size
19, 20, or 21 bits
3
3
The calibration feature is only available using the VertiCal assembly. The default
calibration address bus is 19 bits muxed with CAL_ADDR[12:30]. However, it can
be configured to use CAL_ADDR[10:11] of the muxed signals
CAL_CS[2:3]_CAL_ADDR[10:11] to increase the calibration bus size to the
maximum allowable width on this device of 21 bits.
Table 12-3. Data Bus Size in MPC5565
Bus 324 BGA
EBI data bus size
32 bits
1
1
Although the device is designed to support a 32-bit EBI
data bus, the 324 package only supplies 16 balls for the
EBI data bus (DATA[0:15]).
Calibration data bus size
16 bits
2
2
The calibration feature is only available using the
VertiCal assembly. Although the device is designed to
support calibration, the 324 package does not provide
balls for this feature.