Freescale Semiconductor MPC5565, Reference Manual

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Reset
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 4-3
4.2.3 Reset Configuration (RSTCFG)
The RSTCFG input is used to enable the BOOTCFG[0:1] and PLLCFG[0:1] pins during reset. If RSTCFG
is negated during reset, the BOOTCFG and PLLCFG pins are not sampled at the negation of RSTOUT. In
that case, the default values for BOOTCFG and PLLCFG are used. If RSTCFG is asserted during reset,
the values on the BOOTCFG and PLLCFG pins are sampled and configure the boot and FMPLL modes.
4.2.4 Weak Pull Configuration (WKPCFG)
WKPCFG determines whether specified eTPU and EMIOS pins are connected to a weak pullup or weak
pulldown during and immediately after reset.
4.2.5 Boot Configuration (BOOTCFG[0:1])
BOOTCFG determines the function and state of the following pins after execution of the BAM reset:
CS[0:3], ADDR[8:31], DATA[0:31], RD_WR, BDIP, WE[0:3], OE, TS, TA, TEA.
Refer to the boot modes detailed in Section 6.4.1.1, “Boot Configuration ” and in Table 6-138 .
4.3 Memory Map/Register Definition
Table 4-1 summarizes the reset controller registers. The base address of the system integration unit is
0xC3F9_0000.
4.3.1 Register Descriptions
This section describes all the reset controller registers. It includes details about the fields in each register,
the number of bits per field, the reset value of the register, and the function of the register.
4.3.1.1 Reset Status Register (SIU_RSR)
The reset status register (SIU_RSR) reflects the most recent source, or sources, of reset. This register
contains one bit for each reset source. A bit set to logic 1 indicates the type of reset that occurred.
Simultaneous reset requests cause more than one bit to be set at the same time. After it is set, the reset
source bits in the SIU_RSR remain set until another reset occurs. The SERF bit is set when a software
external reset occurs, but no previously set bits in the SIU_RSR are cleared.
Refer to Section 4.3.1.1, “Reset Status Register (SIU_RSR) ” for additional information.
The SIU_RSR also contains the values latched at the last reset on the WKPCFG and BOOTCFG[0:1] pins
and a RESET input pin glitch flag. The reset glitch flag bit (RGF) is cleared by writing a 1 to the bit. A
write of 0 has no effect on the bit state. The SIU_RSR can be read at all times.
Table 4-1. Reset Controller Memory Map
Address Register Name Register Description Bits
Base + 0x000C SIU_RSR Reset status register 32
Base + 0x0010 SIU_SRCR System reset control register 32