Freescale Semiconductor MPC5565, Reference Manual

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System Integration Unit (SIU)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
6-114 Freescale Semiconductor
6.3.1.161 Compare B Register Low (SIU_CBRL)
The SIU_CBRL holds the 32-bit value that is compared against the value in the SIU_CARL. The CMPBL
field is read/write and is reset by the synchronous reset signal.
Figure 6-157. Compare B Register Low (SIU_CBRL)
6.4 Functional Description
The following sections provide an functional overview of the SIU operation.
6.4.1 System Configuration
The following sections describe the system configuration.
6.4.1.1 Boot Configuration
The BOOTCFG[0:1] pins determine the boot mode initiated by the BAM program, and whether external
arbitration is selected for external booting. The BAM program uses the BOOTCFG[0] to determine where
to read the reset configuration halfword (RCHW), and whether to initiate a FlexCAN or eSCI boot.
Table 6-138 defines the boot modes specified by the BOOTCFG[0:1] pins. If the RSTCFG pin is asserted
during the assertion of RSTOUT, except in the case of a software external reset, the BOOTCFG pins are
latched 4 clock cycles prior to the negation of the RSTOUT pin and are used to update the SIU_RSR and
the BAM boot mode. Otherwise, if RSTCFG is negated during the assertion of RSTOUT, the BOOTCFG
pins are ignored and the boot mode defaults to ‘Boot from internal flash memory.’
Refer to Section 15.3.2.2.4, “Read the Reset Configuration Halfword ” for details on the RCHW.
Address: Base + 0x0994 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
CMPBL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CMPBL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 6-138. BOOTCFG[0:1] Configuration
Value Meaning
0b00 Boot from internal flash memory
0b01 FlexCAN/eSCI boot
0b10 Boot from external memory (no arbitration)
0b11 Boot from external memory (external arbitration)