32.2.2 Entering Sleep mode
To enter Sleep mode, write 1 to CR[SLP].
32.3 Memory map and register definition
This section describes the RNGA registers.
RNG memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4002_9000 RNGA Control Register (RNG_CR)
32
R/W
0000_0000h
4002_9004 RNGA Status Register (RNG_SR)
32
R
0001_0000h
4002_9008 RNGA Entropy Register (RNG_ER)
32
W
(always
reads 0)
0000_0000h
4002_900C RNGA Output Register (RNG_OR)
32
R
0000_0000h
32.3.1 RNGA Control Register (RNG_CR)
Controls the operation of RNGA.
Address: 4002_9000h base + 0h offset = 4002_9000h
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Chapter 32 Random Number Generator Accelerator (RNGA)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
683