SIM_SCGC7 field descriptions (continued)
Field
Description
1
DMA
DMA Clock Gate Control
This bit controls the clock gate to the DMA module.
0
Clock disabled
1
Clock enabled
0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12.2.13 System Clock Divider Register 1 (SIM_CLKDIV1)
When updating CLKDIV1, update all fields using the one write command. Attempting to
write an invalid clock ratio to the CLKDIV1 register will cause the write to be ignored.
The maximum divide ratio that can be programmed between core/system clock and the
other divided clocks is divide by 8. When OUTDIV1 equals 0000 (divide by 1), the other
dividers cannot be set higher than 0111 (divide by 8).
NOTE
The CLKDIV1 register cannot be written to when the device is
in VLPR mode.
Address: 4004_7000h base + 1044h offset = 4004_8044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 1* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*
* Notes:
Reset value loaded during Syetem Reset from FTF_FOPT[LPBOOT].
•
SIM_CLKDIV1 field descriptions
Field
Description
31–28
OUTDIV1
Clock 1 output divider value
This field sets the divide value for the core/system clock from MCGOUTCLK. At the end of reset, it is
loaded with either 0000 or 0111 depending on FTF_FOPT[LPBOOT].
0000
Divide-by-1.
0001
Divide-by-2.
0010
Divide-by-3.
0011
Divide-by-4.
0100
Divide-by-5.
0101
Divide-by-6.
0110
Divide-by-7.
Table continues on the next page...
Chapter 12 System Integration Module (SIM)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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