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MCIMX53SMD Board Hardware User’s Guide, Rev. 0
Freescale Semiconductor
5.3.5
Watch Dog Timer
The i.MX53 processor has an internal Watch Dog Timer circuit. On the MCIMX53SMD board, the WDOG
output is assigned to GPIO_9. The WDOG is an active low signal. The Dialog PMIC does not have a specific pin
to accept a Watch Dog signal to force a processor reset. Therefore, the WDOG signal is modified by hardware
components on the MCIMX53SMD board and applied to the Processor Reset pin (POR_B, pin C19). It allows
the processor to reset the WDOG signal and then come out of reset. The buffer IC is also in a tri-state
condition when the WDOG signal is normally high, thus allowing the push-button reset circuitry to work. The
Watch Dog circuitry is shown in
Figure 5-5
.
Figure 5-5.
Watch Dog Timer Reset Trigger
5.4.
DDR3 SDRAM Memory
The MCIMX53SMD board has four 128MX16 DDR3 SDRAM chips for a total of 1 GB RAM memory. The chips
are organized in two different arrays, differentiated by the chip selects, storing either the upper 16-bits or the
lower 16-bits of a 32-bit word. This organization is shown in
Table 5-6
.
Chip Select ‘0’
Chip Select ‘1’
Lower 16-bits [15:0]
U3
U4
Upper 16-bits [31:16]
U5
U6
Table 5-6.
DDR3 SDRAM Chip Organization
In this organization, there are 21 traces that connect to all four DDR3 chips and the i.MX53 processor (14
Address, 3 Bank Address, 3 Control, and Reset). These are the most critical traces since they will see the most
loading. The remaining traces are connected to two DDR3 chips and the processor, and will only see one active
DDR3 chip at a time. Note that the two clock traces are tied with the data traces (SDCLK_0 for the lower 16-
bits, SDCLK_1 for the upper 16-bits). This limits the clock traces to only one active DDR3 chip at a time.
In the physical layout, the DDR3 chips are placed to minimize routing of the address traces. The two chip select
‘0’ chips are placed on top, and the two chip select ‘1’ chips are placed on the bottom side, directly below the
chips with the same data traces. The data traces are not necessarily connected to the DDR3 chips in sequential
order, but for ease of routing, are connected as best determined by the layout and other critical traces. The
i.MX53 processor has the capability of remapping SDRAM word bit order based on chip select used, so that
words can be physically stored in memory in correct order. If this is a feature the developer wishes to
implement, there is more information in the software reference manual.
The DDR_VREF is created by a simple voltage divider using 470Ω 1% resistors and 0.1 µF capacitors for
stability. The relatively small value resistors provide enough current to maintain a steady mid-point voltage.
The calibration resistors used by the four DDR3 chips and the processor are 240Ω 1% resistors. This resistor
value is specified by the DDR3 specifications. There is a 200Ω resistor between each clock differential pair to
