Freescale Semiconductor MC9S12ZVM series, Reference Manual

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Chapter 2 Port Integration Module (S12ZVMPIMV1)
MC9S12ZVM Family Reference Manual Rev. 1.3
112 Freescale Semiconductor
2.4.3 Pin I/O Control
Figure 2-24 illustrates the data paths to and from an I/O pin. Input and output data can always be read via
the input register (PTIx, Section 2.3.3.2, “Port Input Register ”) independent if the pin is used as general-
purpose I/O or with a shared peripheral function. If the pin is configured as input (DDRx=0,
Section 2.3.3.3, “Data Direction Register ”), the pin state can also be read through the data register (PTx,
Section 2.3.3.1, “Port Data Register ”).
The general-purpose data direction configuration can be overruled by an enabled peripheral function
shared on the same pin (
Table 2-23 ). If more than one peripheral function is available and enabled at the
same time, the highest ranked module according the predefined priority scheme in Table 2-1 will take
precedence on the pin.
ADCx ANx_y None
2 (4)
None
3
VRH, VRL
AMPx AMPx, AMPPx, AMPMx None
2 4
None
3
IRQ IRQ Forced input None
3
XIRQ XIRQ Forced input None
3
LINPHY0 LPTXD0 Forced input None
3
LPRXD0 Forced output Forced off
1. If applicable the appropriate routing configuration must be set for the signals to take effect on the pins.
2. DDR maintains control
3. PER/PPS maintain control
4. To use the digital input function the related bit in Digital Input Enable Register (DIENADx) must be set to logic
level “1”.
Table 2-23. Effect of Enabled Features
Enabled
Feature
(1)
Related Signal(s)
Effect on
I/O state
Effect on enabled
pull device