Freescale Semiconductor MC9S12ZVM series, Reference Manual

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Chapter 2 Port Integration Module (S12ZVMPIMV1)
MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor 103
2.3.3.3 Data Direction Register
This is a generic description of the standard data direction registers. Refer to Table 2-22 to determine the
implemented bits in the respective register. Unimplemented bits read zero.
Table 2-10. Port Input Register Field Descriptions
Field Description
7-0
PTIx7-0
Port Input — Data input
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Address 0x0264 DDRE
0x0284 DDRADH
0x0285 DDRADL
0x02C2 DDRT
0x02D2 DDRS
0x02F2 DDRP
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime
7 6 5 4 3 2 1 0
R
DDRx7 DDRx6 DDRx5 DDRx4 DDRx3 DDRx2 DDRx1 DDRx0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-12. Data Direction Register
Table 2-11. Data Direction Register Field Descriptions
Field Description
7-0
DDRx7-0
Data Direction — Select general-purpose data direction
This bit determines whether the pin is a general-purpose input or output. If a peripheral module controls the pin the
content of the data direction register is ignored. Independent of the pin usage with a peripheral module this register
determines the source of data when reading the associated data register address.
Note: Due to internal synchronization circuits, it can take up to two bus clock cycles until the correct value is read
on port data and port input registers, when changing the data direction register.
1 Associated pin is configured as output
0 Associated pin is configured as input