Chapter 20 ECC Generation module (SRAM_ECCV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
683
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Figure 20-9. 2 byte non-aligned write access
20.3.3
Memory read access
During each memory read access an ECC check is performed. If the logic detects a single bit ECC error
then the module corrects the data, so that the access initiator module receives correct data. In parallel, the
logic writes the corrected data back to the memory, so that this read access repairs the single bit ECC error.
This automatic ECC read repair function is disabled by setting the ECCDRR bit.
If a single bit ECC error was detected then the SBEEIF flag is set.
If the logic detects a double bit ECC error, then the data word is flagged as invalid, so that the access
initiator module can ignore the data.
20.3.4
Memory initialization
Memory operation which allows a read before a first write, like the read-modify-write operation of the un-
aligned access, requires that the memory contains valid ECC values before the first read-modify-write
access is performed to avoid spurious ECC error reporting. The ECC module provides logic to initialize
the complete memory content with zero during the power up phase. During the initialization process the
access to the SRAM is disabled and the RDY status bit is cleared. If the initialization process is done, the
SRAM access is possible and the RDY status bit is set.
20.3.5
Interrupt handling
This sections describes the interrupts generated by the SRAM_ECC module and their individual sources,
Vector addresses and interrupt priority are defined by MCU level.
ECC
2 byte use data
correct read data
read out data
and correct if
single bit ECC
error was found
write data
ECC
correct
read data write data
ECC
2 byte use data
correct read data
read out data
and correct if
single bit ECC
error was found
write data
ECC
correct
read data
write data
4 byte write data to system memory
4 byte read data from system memory
2 byte write data
