Freescale Semiconductor MC68HC908MR16 Datasheet Download Page 264

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MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

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Freescale Semiconductor

Figure 18-13. Monitor Mode Entry Timing

BYTE 1

TE 1

BYTE 2

TE 2

BYTE 8

BYTE 8 ECHO

COMMAND

ECHO

PA0

PA7

RST

4096 + 32 CGMXCLK CYCLES

24 BUS CYCLES

256 BUS CYCLES (MINIMUM)

BREAK

NOTES:

2 = Data return delay, 2 bit times
3 = Wait 1 bit time before sending next byte.

FROM HOST

FROM MCU

1 = Echo delay, 2 bit times

Summary of Contents for MC68HC908MR16

Page 1: ...M68HC08 Microcontrollers freescale com MC68HC908MR32 MC68HC908MR16 Data Sheet MC68HC908MR32 Rev 6 1 07 2005...

Page 2: ......

Page 3: ...SuperFlash technology licensed from SST Freescale Semiconductor Inc 2005 All rights reserved MC68HC908MR32 MC68HC908MR16 Data Sheet To provide the most up to date information the revision of our docu...

Page 4: ...circuitry added 279 Table 18 2 Monitor Mode Signal Requirements and Options Switch locations added to column headings for clarity 281 Section 16 Timer Interface A TIMA Timer discrepancies corrected t...

Page 5: ...RQ 91 Chapter 9 Low Voltage Inhibit LVI 97 Chapter 10 Input Output I O Ports PORTS 101 Chapter 11 Power On Reset POR 113 Chapter 12 Pulse Width Modulator for Motor Control PWMMC 115 Chapter 13 Serial...

Page 6: ...List of Chapters MC68HC908MR32 MC68HC908MR16 Data Sheet Rev 6 1 6 Freescale Semiconductor...

Page 7: ...A7 PTA0 23 1 4 11 Port B I O Pins PTB7 ATD7 PTB0 ATD0 23 1 4 12 Port C I O Pins PTC6 PTC2 and PTC1 ATD9 PTC0 ATD8 23 1 4 13 Port D Input Only Pins PTD6 IS3 PTD4 IS1 and PTD3 FAULT4 PTD0 FAULT1 23 1 4...

Page 8: ...0 3 6 4 ADC Voltage Reference Low Pin VREFL 50 3 6 5 ADC Voltage In ADVIN 51 3 6 6 ADC External Connections 51 3 6 6 1 VREFH and VREFL 51 3 6 6 2 ANx 51 3 6 6 3 Grounding 51 3 7 I O Registers 51 3 7 1...

Page 9: ...ming Register 68 4 6 Interrupts 69 4 7 Wait Mode 69 4 8 Acquisition Lock Time Specifications 70 4 8 1 Acquisition Lock Time Definitions 70 4 8 2 Parametric Influences on Reaction Time 70 4 8 3 Choosin...

Page 10: ...ode 83 7 5 2 Stop Mode 83 7 6 CPU During Break Interrupts 83 7 7 Instruction Set Summary 84 7 8 Opcode Map 89 Chapter 8 External Interrupt IRQ 8 1 Introduction 91 8 2 Features 91 8 3 Functional Descri...

Page 11: ...er F 110 Chapter 11 Power On Reset POR 11 1 Introduction 113 11 2 Functional Description 113 Chapter 12 Pulse Width Modulator for Motor Control PWMMC 12 1 Introduction 115 12 2 Features 115 12 3 Timeb...

Page 12: ...4 12 10 PWM Glossary 155 Chapter 13 Serial Communications Interface Module SCI 13 1 Introduction 157 13 2 Features 157 13 3 Functional Description 159 13 3 1 Data Format 160 13 3 2 Transmitter 161 13...

Page 13: ...4 3 2 3 Illegal Opcode Reset 186 14 3 2 4 Illegal Address Reset 186 14 3 2 5 Forced Monitor Mode Entry Reset MENRST 186 14 3 2 6 Low Voltage Inhibit LVI Reset 186 14 4 SIM Counter 186 14 4 1 SIM Count...

Page 14: ...r 210 15 12 2 SPI Status and Control Register 212 15 12 3 SPI Data Register 214 Chapter 16 Timer Interface A TIMA 16 1 Introduction 215 16 2 Features 215 16 3 Functional Description 219 16 3 1 TIMA Co...

Page 15: ...ns PTE1 TCH0B PTE2 TCH1B 243 17 7 I O Registers 244 17 7 1 TIMB Status and Control Register 244 17 7 2 TIMB Counter Registers 246 17 7 3 TIMB Counter Modulo Registers 246 17 7 4 TIMB Channel Status an...

Page 16: ...ctional Operating Range 266 19 4 Thermal Characteristics 266 19 5 DC Electrical Characteristics 267 19 6 FLASH Memory Characteristics 268 19 7 Control Timing 268 19 8 Serial Peripheral Interface Chara...

Page 17: ...of FLASH program memory MC68HC908MR32 32 Kbytes MC68HC908MR16 16 Kbytes On chip programming firmware for use with host personal computer FLASH data security 1 768 bytes of on chip random access memory...

Page 18: ...supports setting the in circuit simulator ICS single break point Features of the CPU08 include Enhanced M68HC05 programming model Extensive loop control functions 16 addressing modes eight more than...

Page 19: ...TD DDRE PTE PTF DDRF INTERNAL BUS OSC1 OSC2 CGMXFC RST IRQ VSS VDD VDDAD PTA7 PTA0 PTE7 TCH3A PTE6 TCH2A PTE5 TCH1A PTE4 TCH0A PTE3 TCLKA PTE2 TCH1B 1 PTE1 TCH0B 1 PTE0 TCLKB 1 PTF5 TxD PTF4 RxD PTF3...

Page 20: ...H PTC2 PTC3 PTC4 PTC5 IRQ PTF5 TxD PTF4 RxD PTF3 MISO PTF2 MOSI PTF1 SS PTF0 SPSCK VDD PTE7 TCH3A PTE6 TCH2A PTE5 TCH1A PTE4 TCH0A PTE3 TCLKA PTE2 TCH1B PTE1 TCH0B PTA1 PTA0 V SSAD OSC2 OSC1 CGMXFC V...

Page 21: ...0 29 PTA3 PTA4 PTA5 PTA6 PTA7 PTB0 ATD0 PTB1 ATD1 PTB2 ATD2 PTB3 ATD3 PTB4 ATD4 PTB5 ATD5 PTB6 ATD5 PTB7 ATD7 PTC0 ATD8 VDDAD VSSAD VREFL VREFH PTC2 PTC3 PTC4 PTC5 PTC6 PTD0 FAULT1 PTD1 FAULT2 PTD2 FA...

Page 22: ...ypassing 1 4 2 Oscillator Pins OSC1 and OSC2 The OSC1 and OSC2 pins are the connections for the on chip oscillator circuit For more detailed information see Chapter 4 Clock Generator Module CGM 1 4 3...

Page 23: ...O Pins PTB7 ATD7 PTB0 ATD0 Port B is an 8 bit special function port that shares all eight pins with the analog to digital converter ADC See Chapter 3 Analog to Digital Converter ADC and Chapter 10 Inp...

Page 24: ...bit special function port that shares its pins with the two timer interface modules TIMA and TIMB See Chapter 16 Timer Interface A TIMA Chapter 17 Timer Interface B TIMB and Chapter 10 Input Output I...

Page 25: ...ly the write function is unimplemented Writing to a read only I O bit has no effect on microcontroller unit MCU operation In register figures the write function of read only bits is shaded Similarly s...

Page 26: ...t status register SRSR FE03 SIM break flag control register SBFCR FE07 FLASH control register FLCR FE0C Break address register high BRKH FE0D Break address register low BRKL FE0E Break status and cont...

Page 27: ...TER SBFCR FE04 RESERVED FE05 RESERVED FE06 RESERVED FE07 RESERVED FE08 FLASH CONTROL REGISTER FLCR FE09 UNIMPLEMENTED FE0A UNIMPLEMENTED FE0B UNIMPLEMENTED FE0C SIM BREAK ADDRESS REGISTER HIGH BRKH FE...

Page 28: ...0 0 0005 Data Direction Register B DDRB See page 105 Read DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 Write Reset 0 0 0 0 0 0 0 0 0006 Data Direction Register C DDRC See page 106 Read 0 DDRC6 DDRC...

Page 29: ...AX Write 0 Reset 0 0 0 0 0 0 0 0 0014 TIMA Channel 0 Register High TACH0H See page 232 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset Indeterminate after reset 0015 TIMA Channe...

Page 30: ...See page 74 Read EDGE BOTNEG TOPNEG INDEP LVIRST LVIPWR STOPE COPD Write Reset 0 0 0 0 1 1 0 0 0020 PWM Control Register 1 PCTL1 See page 146 Read DISX DISY PWMINT PWMF ISENS1 ISENS0 LDOK PWMEN Write...

Page 31: ...it 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 002C PWM 2 Value Register High PVAL2H See page 145 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 002D PWM 2 Value Regist...

Page 32: ...gister DISMAP See page 137 Read Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset 1 1 1 1 1 1 1 1 0038 SCI Control Register 1 SCC1 See page 169 Read LOOPS ENSCI TXINV M WAKE ILTY PEN PTY Wri...

Page 33: ...gister ADCLK See page 55 Read ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 0 0 Write R Reset 0 0 0 0 0 1 0 0 0044 SPI Control Register SPCR See page 211 Read SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE Write Res...

Page 34: ...7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset Indeterminate after reset 0059 TIMB Channel 1 Status Control Register TBSC1 See page 247 Read CH1F CH1IE 0 MS1A ELS1B ELS1A TOV1 CH1MAX Write 0...

Page 35: ...set 0 0 0 0 0 0 0 0 FE0D Break Address Register Low BRKL See page 254 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 FE0E Break Status and Control Register BRKSCR See page 254 Read BRKE BRKA...

Page 36: ...SPI receive vector low 1 FFDC A D vector high FFDD A D vector low FFDE TIMB overflow vector high FFDF TIMB overflow vector low FFE0 TIMB channel 1 vector high FFE1 TIMB channel 1 vector low FFE2 TIMB...

Page 37: ...d user data or code When the stack pointer is moved from its reset location at 00FF direct addressing mode instructions can access efficiently all page zero RAM locations Page zero RAM therefore provi...

Page 38: ...LASH array is organized into two rows per page The page size is 128 bytes per page The minimum erase page size is 128 bytes Programming is performed on a row basis 64 bytes at a time The address range...

Page 39: ...be equal to 1 or set to 1 at the same time 1 Program operation selected 0 Program operation unselected 2 8 2 FLASH Page Erase Operation Use this step by step procedure to erase a page 128 bytes of FLA...

Page 40: ...MErase minimum 4 ms 7 Clear the ERASE and MASS bits NOTE Mass erase is disabled whenever any block is protected FLBPR does not equal FF 8 Wait for a time tNVHL minimum 100 s 9 Clear the HVEN bit 10 Af...

Page 41: ...hin the row are programmed 10 Clear the PGM bit 1 11 Wait for time tNVH minimum 5 s 12 Clear the HVEN bit 13 After time tRCV typical 1 s the memory can be accessed in read mode again NOTE The COP regi...

Page 42: ...OGRAMMED WAIT FOR A TIME tPROG CLEAR PGM BIT WAIT FOR A TIME tNVH CLEAR HVEN BIT WAIT FOR A TIME tRCV COMPLETED PROGRAMMING THIS ROW YES NO END OF PROGRAMMING The time between each FLASH address chang...

Page 43: ...e the FLBPR is programmed with a value other than FF any erase or program of the FLBPR or the protected block of FLASH memory is prohibited Mass erase is disabled whenever any block is protected FLBPR...

Page 44: ...ASH memory directly but there will not be any memory activity since the CPU is inactive The STOP instruction should not be executed while performing a program or erase operation on the FLASH otherwise...

Page 45: ...tified result Left justified sign data mode High impedance buffered ADC input 3 3 Functional Description Ten ADC channels are available for sampling external sources at pins PTC1 ATD9 PTC0 ATD8 and PT...

Page 46: ...RA DDRB PTB DDRC PTC PTD DDRE PTE PTF DDRF INTERNAL BUS OSC1 OSC2 CGMXFC RST IRQ VSS VDD VDDAD PTA7 PTA0 PTE7 TCH3A PTE6 TCH2A PTE5 TCH1A PTE4 TCH0A PTE3 TCLKA PTE2 TCH1B 1 PTE1 TCH0B 1 PTE0 TCLKB 1 P...

Page 47: ...ffect on the port pin that is selected by the ADC Read of a port pin which is in use by the ADC will return a 0 3 3 2 Voltage Conversion When the input voltage to the ADC equals VREFH the ADC converts...

Page 48: ...and is represented as the 17th cycle 3 3 4 Continuous Conversion In continuous conversion mode the ADC data registers ADRH and ADRL will be filled with new data after each conversion Data from the pre...

Page 49: ...mid scale is needed Finally 8 bit truncation mode will place the eight MSBs in ADC data register low ADRL The two LSBs are dropped This mode of operation is used when compatibility with 8 bit ADC desi...

Page 50: ...AD as its power pin Connect the VDDAD pin to the same voltage potential as VDD External filtering may be necessary to ensure clean VDDAD for good results NOTE Route VDDAD carefully for maximum noise i...

Page 51: ...placed as close as possible to the package pins Resistance in the path is not recommended because the dc current will cause a voltage drop which could result in conversion errors 3 6 6 2 ANx Empirica...

Page 52: ...is cleared when the data register is read or the status control register is written Reset clears the AIEN bit 1 ADC interrupt enabled 0 ADC interrupt disabled ADCO ADC Continuous Conversion Bit When...

Page 53: ...PTB0 ATD0 0 0 0 0 1 PTB1 ATD1 0 0 0 1 0 PTB2 ATD2 0 0 0 1 1 PTB3 ATD3 0 0 1 0 0 PTB4 ATD4 0 0 1 0 1 PTB5 ATD5 0 0 1 1 0 PTB6 ATD6 0 0 1 1 1 PTB7 ATD7 0 1 0 0 0 PTC0 ATD8 0 1 0 0 1 PTC1 ATD9 1 1 ATD9...

Page 54: ...lt All other bits read as 0 This register is updated each time a single channel ADC conversion completes Reading ADRH latches the contents of ADRL until ADRL is read Until ADRL is read all subsequent...

Page 55: ...3 2 shows the available clock configurations Address 0042 Bit 7 6 5 4 3 2 1 Bit 0 Read AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Write R R R R R R R R Reset Unaffected by reset R Reserved Figure 3 8 ADC Data Re...

Page 56: ...the PLL generated bus clock as the clock source As long as the internal ADC clock is at fADIC correct operation can be guaranteed See 19 13 Analog to Digital Converter ADC Characteristics 1 Internal b...

Page 57: ...lock 4 2 Features Features of the CGM include PLL with output frequency in integer multiples of the crystal reference Programmable hardware voltage controlled oscillator VCO for low jitter operation A...

Page 58: ...e R R R R R Reset 0 0 0 0 0 0 0 0 005E PLL Programming Register PPG See page 68 Read MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4 Write Reset 0 1 1 0 0 1 1 0 R Reserved Figure 4 2 CGM I O Register Summary...

Page 59: ...ector The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise including supply and CGMXFC noise The VCO frequency is bound to a range...

Page 60: ...switches between acquisition and tracking modes Automatic bandwidth control mode also is used to determine when the VCO clock CGMVCLK is safe to use as the source for the base clock CGMOUT See 4 5 2 P...

Page 61: ...PLL as the clock source to CGMOUT BCS 1 The LOCK bit is disabled CPU interrupts from the CGM are disabled 4 3 2 4 Programming the PLL Use this 9 step procedure to program the PLL Table 4 1 lists the v...

Page 62: ...f N b In the lower four bits of the PLL programming register PPG program the binary equivalent of L 4 3 2 5 Special Programming Exceptions The programming method described in 4 3 2 4 Programming the P...

Page 63: ...he source of the base clock 4 3 4 CGM External Connections In its typical configuration the CGM requires seven external components Five of these are for the crystal oscillator and two are for the PLL...

Page 64: ...in OSC2 The OSC2 pin is the output of the crystal oscillator inverting amplifier 4 4 3 External Filter Capacitor Pin CGMXFC The CGMXFC pin is required by the loop filter to filter out phase correction...

Page 65: ...is the interrupt signal generated by the PLL lock detector 4 5 CGM Registers These registers control and monitor operation of the CGM PLL control register PCTL see 4 5 1 PLL Control Register PLL bandw...

Page 66: ...n on the PLL control register clears the PLLF bit PLLON PLL On Bit This read write bit activates the PLL and enables the VCO clock CGMVCLK PLLON cannot be cleared if the VCO clock is driving the base...

Page 67: ...e ACQ bit before turning on the PLL Reset clears the AUTO bit 1 Automatic bandwidth control 0 Manual bandwidth control LOCK Lock Indicator Bit When the AUTO bit is set LOCK is a read only bit that bec...

Page 68: ...systems to user applications software should write 0s to PBWC 3 0 whenever writing to PBWC 4 5 3 PLL Programming Register The PLL programming register PPG contains the programming information for the...

Page 69: ...nterrupt request every time the LOCK bit changes state The PLLIE bit in the PLL control register PCTL enables CPU interrupts from the PLL PLLF the interrupt flag in the PCTL becomes set whether interr...

Page 70: ...within a certain tolerance of the desired frequency regardless of the size of the initial error The discrepancy in these definitions makes it difficult to specify an acquisition or lock time for a typ...

Page 71: ...ternal factors however can cause drastic changes in the operation of the PLL These factors include noise injected into the PLL through the filter capacitor filter capacitor leakage stray impedances on...

Page 72: ...ain that the PLL is within the tracking mode entry tolerance TRK before exiting acquisition mode A certain number of clock cycles nTRK is required to ascertain that the PLL is within the lock mode ent...

Page 73: ...ch reset All of the configuration register bits are cleared during reset Since the various options affect the operation of the microcontroller unit MCU it is recommended that this register be written...

Page 74: ...EP determines if the motor control PWMs will be six independent PWMs or three complementary PWM pairs See Chapter 12 Pulse Width Modulator for Motor Control PWMMC 1 Six independent PWMs 0 Three comple...

Page 75: ...ay code Prevent a COP reset by periodically clearing the COP counter 6 2 Functional Description Figure 6 1 shows the structure of the COP module A summary of the input output I O register is shown in...

Page 76: ...ven while the main program is not working properly 6 3 I O Signals This section describes the signals shown in Figure 6 1 6 3 1 CGMXCLK CGMXCLK is the crystal oscillator output signal CGMXCLK frequenc...

Page 77: ...et vector 6 5 Interrupts The COP does not generate CPU interrupt requests 6 6 Monitor Mode The COP is disabled in monitor mode when VHI is present on the IRQ pin or on the RST pin 6 7 Wait Mode The WA...

Page 78: ...Computer Operating Properly COP MC68HC908MR32 MC68HC908MR16 Data Sheet Rev 6 1 78 Freescale Semiconductor...

Page 79: ...mpatible with M68HC05 Family 16 bit stack pointer with stack manipulation instructions 16 bit index register with x register manipulation instructions 8 MHz CPU internal bus frequency 64 Kbyte program...

Page 80: ...ndex register In the indexed addressing modes the CPU uses the contents of the index register to determine the conditional address of the operand The index register can serve also as a temporary data...

Page 81: ...ccess memory RAM Moving the SP out of page 0 0000 to 00FF frees direct address page 0 space For correct operation the stack pointer must point only to RAM locations 7 3 4 Program Counter The program c...

Page 82: ...upt mask is set all maskable CPU interrupts are disabled CPU interrupts are enabled when the interrupt mask is cleared When a CPU interrupt occurs the interrupt mask is set automatically after the CPU...

Page 83: ...de The WAIT instruction Clears the interrupt mask I bit in the condition code register enabling interrupts After exit from wait mode by interrupt the I bit remains clear After exit by reset the I bit...

Page 84: ...D opr SP Logical AND A A M 0 IMM DIR EXT IX2 IX1 IX SP1 SP2 A4 B4 C4 D4 E4 F4 9EE4 9ED4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ASL opr ASLA ASLX ASL opr X ASL X ASL opr SP Arithmetic Shift Left...

Page 85: ...A rel Branch Always PC PC 2 rel REL 20 rr 3 BRCLR n opr rel Branch if Bit n in M Clear PC PC 3 rel Mn 0 DIR b0 DIR b1 DIR b2 DIR b3 DIR b4 DIR b5 DIR b6 DIR b7 01 03 05 07 09 0B 0D 0F dd rr dd rr dd r...

Page 86: ...ff ff ff ee ff 2 3 4 4 3 2 4 5 DAA Decimal Adjust A A 10 U INH 72 2 DBNZ opr rel DBNZA rel DBNZX rel DBNZ opr X rel DBNZ X rel DBNZ opr SP rel Decrement and Branch if Not Zero A A 1 or M M 1 or X X 1...

Page 87: ...Same as ASL DIR INH INH IX1 IX SP1 38 48 58 68 78 9E68 dd ff ff 4 1 1 4 3 5 LSR opr LSRA LSRX LSR opr X LSR X LSR opr SP Logical Shift Right 0 DIR INH INH IX1 IX SP1 34 44 54 64 74 9E64 dd ff ff 4 1 1...

Page 88: ...A A M C IMM DIR EXT IX2 IX1 IX SP1 SP2 A2 B2 C2 D2 E2 F2 9EE2 9ED2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 SEC Set Carry Bit C 1 1 INH 99 1 SEI Set Interrupt Mask I 1 1 INH 9B 2 STA opr STA opr...

Page 89: ...ative program counter offset byte DIX Direct to indexed with post increment addressing mode rr Relative program counter offset byte ee ff High and low bytes of offset in indexed 16 bit offset addressi...

Page 90: ...4 3 DIR 4 BSET4 2 DIR 3 BHCC 2 REL 4 LSL 2 DIR 1 LSLA 1 INH 1 LSLX 1 INH 4 LSL 2 IX1 5 LSL 3 SP1 3 LSL 1 IX 2 PULX 1 INH 1 CLC 1 INH 2 EOR 2 IMM 3 EOR 2 DIR 4 EOR 3 EXT 4 EOR 3 IX2 5 EOR 4 SP2 3 EOR 2...

Page 91: ...Functional Description A logic 0 applied to any of the external interrupt pins can latch a CPU interrupt request Figure 8 1 shows the structure of the IRQ module Figure 8 1 IRQ Module Block Diagram Ad...

Page 92: ...is low the interrupt request remains pending When set the IMASK1 bit in the ISCR masks all external interrupt requests A latched interrupt request is not presented to the interrupt priority logic unl...

Page 93: ...emiconductor 93 Figure 8 3 IRQ Interrupt Flowchart FROM RESET I BIT SET FETCH NEXT YES NO INTERRUPT INSTRUCTION SWI INSTRUCTION RTI INSTRUCTION NO STACK CPU REGISTERS NO SET I BIT LOAD PC WITH INTERRU...

Page 94: ...with the vector address at locations FFFA and FFFB Return of the IRQ pin to logic 1 As long as the IRQ pin is at logic 0 the IRQ1 latch remains set The vector fetch or software clear and the return o...

Page 95: ...terrupt requests disabled 0 IRQ interrupt requests enabled MODE1 IRQ Edge Level Select Bit This read write bit controls the triggering sensitivity of the IRQ pin Reset clears MODE1 1 IRQ interrupt req...

Page 96: ...External Interrupt IRQ MC68HC908MR32 MC68HC908MR16 Data Sheet Rev 6 1 96 Freescale Semiconductor...

Page 97: ...LVI module The LVI is enabled out of reset The LVI module contains a bandgap reference circuit and comparator The LVI power bit LVIPWR enables the LVI to monitor VDD voltage The LVI reset bit LVIRST e...

Page 98: ...MCU when VDD falls to the VLVRX level and remains at or below that level for nine or more consecutive CPU cycles In the CONFIG register the LVIPWR and LVIRST bits must be 1s to enable the LVI module...

Page 99: ...d VLVH2 respectively NOTE If LVIRST and LVIPWR are 0s note that when changing the tolerance LVI reset will be generated if the supply voltage is below the trip point 9 5 LVI Interrupts The LVI module...

Page 100: ...h the LVIRST bit in the configuration register programmed to 1 the LVI module can generate a reset and bring the MCU out of wait mode 9 7 Stop Mode If enabled the LVI module remains active in stop mod...

Page 101: ...d I O pins to an appropriate logic level either VDD or VSS Although PWM6 PWM1 do not require termination for proper operation termination reduces excess current consumption and the possibility of elec...

Page 102: ...ee page 108 Read PTE7 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 Write Reset Unaffected by reset 0009 Port F Data Register PTF See page 110 Read 0 0 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 Write R R Reset Unaffected by...

Page 103: ...A bit enables the output buffer for the corresponding port A pin a logic 0 disables the output buffer DDRA 7 0 Data Direction Register A Bits These read write bits control port A data direction Reset...

Page 104: ...ster PTB contains a data latch for each of the eight port B pins PTB 7 0 Port B Data Bits These read write bits are software programmable Data direction of each port B pin is under the control of the...

Page 105: ...re 10 7 shows the port B I O logic Figure 10 7 Port B I O Circuit When bit DDRBx is a logic 1 reading address 0001 reads the PTBx data latch When bit DDRBx is a logic 0 reading address 0001 reads the...

Page 106: ...C pin is an input or an output Writing a logic 1 to a DDRC bit enables the output buffer for the corresponding port C pin a logic 0 disables the output buffer DDRC 6 0 Data Direction Register C Bits...

Page 107: ...l module PMC The port D data register PTD contains a data latch for each of the seven port pins PTD 6 0 Port D Data Bits These read write bits are software programmable Reset has no effect on port D d...

Page 108: ...Data Bits PTE 7 0 are read write software programmable bits Data direction of each port E pin is under the control of the corresponding bit in data direction register E NOTE Data direction register E...

Page 109: ...e 10 15 shows the port E I O logic Figure 10 15 Port E I O Circuit When bit DDREx is a logic 1 reading address 0008 reads the PTEx data latch When bit DDREx is a logic 0 reading address 0008 reads the...

Page 110: ...rns the states of the latches or the states of the pins 10 7 2 Data Direction Register F Data direction register F DDRF determines whether each port F pin is an input or an output Writing a logic 1 to...

Page 111: ...latch can always be written regardless of the state of its data direction bit Table 10 6 summarizes the operation of the port F pins Table 10 6 Port F Pin Functions DDRF Bit PTF Bit I O Pin Mode Acces...

Page 112: ...Input Output I O Ports PORTS MC68HC908MR32 MC68HC908MR16 Data Sheet Rev 6 1 112 Freescale Semiconductor...

Page 113: ...al to the microcontroller unit MCU at power on This signal tracks VDD until the MCU generates a feedback signal to indicate that it is properly initialized At this time the POR drives its output low T...

Page 114: ...Power On Reset POR MC68HC908MR32 MC68HC908MR16 Data Sheet Rev 6 1 114 Freescale Semiconductor...

Page 115: ...P and a programmable prescaler The highest resolution for edge aligned operation is 125 ns fOP 8 MHz The highest resolution for center aligned operation is 250 ns fOP 8 MHz When generating complementa...

Page 116: ...ER PTA DDRA DDRB PTB DDRC PTC PTD DDRE PTE PTF DDRF INTERNAL BUS OSC1 OSC2 CGMXFC RST IRQ VSS VDD VDDAD PTA7 PTA0 PTE7 TCH3A PTE6 TCH2A PTE5 TCH1A PTE4 TCH0A PTE3 TCLKA PTE2 TCH1B 1 PTE1 TCH0B 1 PTE0...

Page 117: ...FMODE4 FINT3 FMODE3 FINT2 FMODE2 FINT1 FMODE1 Write Reset 0 0 0 0 0 0 0 0 0023 Fault Status Register FSR See page 152 Read FPIN4 FFLAG4 FPIN3 FFLAG3 FPIN2 FFLAG2 FPIN1 FFLAG1 Write Reset U 0 U 0 U 0...

Page 118: ...X X X X X 002A PWM 1 Value Register High PVAL1H See page 145 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 002B PWM 1 Value Register Low PVAL1L See page 145 R...

Page 119: ...7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 0034 PWM 6 Value Register High PVAL6H See page 145 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset 0 0 0...

Page 120: ...s used to create the PWM period Therefore the PWM resolution in center aligned mode is two clocks highest resolution is 250 ns fOP 8 MHz as shown in Figure 12 4 The up down counter uses the value in t...

Page 121: ...resolution is125 ns fOP 8 MHz as shown in Figure 12 5 Again the timer modulus register is used to determine the maximum count The PWM period will equal timer modulus x PWM clock period Center aligned...

Page 122: ...New PWM values counter modulus values and prescalers can be loaded from their buffers into the PWM module every one two four or eight PWM cycles LDFQ1 and LDFQ0 in PWM control register 2 are used to c...

Page 123: ...them an interlock bit controlled from software is provided This bit informs the PWM module that all the PWM parameters have been calculated and it is okay to use them A new modulus prescaler and or PW...

Page 124: ...MODULUS 3 PWM VALUE 2 LDOK 0 MODULUS 3 PWM VALUE 1 PWMF SET PWMF SET PWMF SET PWMF SET LDOK 1 PWM VALUE 1 MODULUS 2 LDOK 1 PWM VALUE 1 MODULUS 3 LDOK 1 PWMVALUE 1 MODULUS 2 LDOK 1 PWM VALUE 1 MODULUS...

Page 125: ...e PWM value is greater than or equal to the timer modulus the PWM will be active for the entire period Refer to Table 12 3 NOTE The terms active and inactive refer to the asserted and negated states o...

Page 126: ...d see 5 2 Functional Description If complementary operation is chosen the PWM pins are paired as shown in Figure 12 12 Operation of one pair is then determined by one PWM value register This type of o...

Page 127: ...or pair to use for the top PWM in the next PWM cycle See 12 5 3 Top Bottom Correction with Motor Phase Current Polarity Sensing When output control is enabled the odd OUT bits rather than the PWM gene...

Page 128: ...TTOM GENERATION POSTDT TOP TOP BOTTOM GENERATION TOP BOTTOM GENERATION TOP BOTTOM TOP BOTTOM TOP BOTTOM PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 6 MUX PWM TOP OUTX SELECT PREDT TOP MUX PWM TOP OUTX SELECT PREDT...

Page 129: ...Dead Time at Duty Cycle Boundaries PWM VALUE 2 PWM VALUE 2 PWM VALUE 3 PWM1 W PWM2 W PWM1 W PWM2 W NO DEAD TIME NO DEAD TIME DEAD TIME 2 DEAD TIME 2 2 2 2 2 UP DOWN COUNTER MODULUS 4 2 2 UP DOWN COUNT...

Page 130: ...er allowed to float and is strictly controlled by the PWM waveforms Figure 12 18 Ideal Complementary Operation Dead Time 0 However when dead time is inserted the motor voltage is allowed to float mome...

Page 131: ...lue register to be used by the PWM generator Current sensing or programmable software bits are then used to determine which PWM value to use If the current sensed at the motor for that PWM pair is pos...

Page 132: ...PWM cycle in center aligned mode and at the end of the cycle in edge aligned mode Therefore even at 0 percent and 100 percent duty cycle the current is sensed Distortion correction is only available i...

Page 133: ...rols the polarity of PWMs 2 4 and 6 Positive polarity means that when the PWM is active the PWM output is high Conversely negative polarity means that when the PWM is active PWM output is low See Figu...

Page 134: ...DOWN COUNTER MODULUS 4 PWM 0 PWM 1 PWM 2 PWM 3 PWM 4 UP ONLY COUNTER MODULUS 4 PWM 0 PWM 1 PWM 2 PWM 3 PWM 4 CENTER ALIGNED POSITIVE POLARITY EDGE ALIGNED POSITIVE POLARITY UP DOWN COUNTER MODULUS 4...

Page 135: ...WM generator and current sensing circuitry They continue to run but are no longer controlling the output pins In addition OUTCTL will control the PWM pins even when PWMEN 0 When OUTCTL is cleared the...

Page 136: ...PART OF NORMAL PWM OPERATION AS CONTROLLED BY CURRENT SENSING AND PWM GENERATOR DEAD TIME INSERTED DUE TO SETTING OF OUT1 BIT DEAD TIME INSERTED DUE TO CLEARING OF OUT1 BIT PWM VALUE 3 DEAD TIME UP DO...

Page 137: ...fault pin 2 and PWM disable bit X constitute the disabling function of bank X Fault pin 3 fault pin 4 and PWM disable bit Y constitute the disabling function of bank Y Figure 12 25 and Figure 12 27 sh...

Page 138: ...ogically similar and affects BANK Y disable Note In manual mode FMODE 0 faults 2 and 4 may be cleared only if a logic level low at the input of the fault pin is present FAULT PIN2 DISABLE TWO SAMPLE F...

Page 139: ...new PWM cycle begins as shown in Figure 12 28 Clearing the corresponding FFLAGx event bit will not enable the PWMs in automatic mode The filtered fault pin s logic state is reflected in the respective...

Page 140: ...vent bit and a new PWM cycle begins In manual mode the fault pins are grouped in pairs each pair sharing common functionality A fault condition on pins 1 and 3 may be cleared allowing the PWM s to ena...

Page 141: ...shown in Figure 12 31 Setting a PWM disable bit does not latch a CPU interrupt request and there are no event flags associated with the PWM disable bits 12 6 3 Output Port Control When operating the P...

Page 142: ...er than the specified value Because of the equals comparator architecture of this PWM the modulus 0 case is considered illegal Therefore the modulus register is not reset and a modulus value of 0 will...

Page 143: ...ower will be reduced because the PWMs will no longer toggle 12 9 Control Logic Block This subsection provides a description of the control logic block 12 9 1 PWM Counter Registers The PWM counter regi...

Page 144: ...t necessarily the value the PWM generator is currently using Because of the equals comparator architecture of this PWM the modulus 0 case is considered illegal Therefore the modulus register is not re...

Page 145: ...period If the complementary mode is selected the PWM pairs share PWM value registers To avoid erroneous PWM pulses this value is buffered and will not be used by the PWM generator until the LDOK bit...

Page 146: ...s in bank Y 0 Re enable PWM pins at beginning of next PWM cycle PWMINT PWM Interrupt Enable Bit This read write bit allows the user to enable and disable PWM CPU interrupts If set a CPU interrupt will...

Page 147: ...CPU interrupt request can still be generated when LDOK is 0 PWMEN PWM Module Enable Bit This read write bit enables and disables the PWM generator and the PWM pins When PWMEN is clear the PWM generat...

Page 148: ...write bits select the PWM CPU load frequency according to Table 12 8 NOTE When reading these bits the value read is the buffer value not necessarily the value the PWM generator is currently using The...

Page 149: ...the buffer value not necessarily the value the output control block is currently using IPOL3 Top Bottom Correction Bit for PWM Pair 3 PWMs 5 and 6 This buffered read write bit selects which PWM value...

Page 150: ...rewritten unless a reset occurs 12 9 8 Fault Control Register The fault control register FCR controls the fault protection circuitry FINT4 Fault 4 Interrupt Enable Bit This read write bit allows the...

Page 151: ...bit allows the CPU interrupt caused by faults on fault pin 2 to be enabled The fault protection circuitry is independent of this bit and will always be active If a fault is detected the PWM pins will...

Page 152: ...t Event Flag 3 The FFLAG3 event bit is set within two CPU cycles after a rising edge on fault pin 3 To clear the FFLAG3 bit the user must write a 1 to the FTACK3 bit in the fault acknowledge register...

Page 153: ...bit will clear FFLAG3 Writing a 0 will have no effect FTACK2 Fault Acknowledge 2 Bit The FTACK2 bit is used to acknowledge and clear FFLAG2 This bit will always read 0 Writing a 1 to this bit will cle...

Page 154: ...tput circuitry When OUTCTL is cleared the outputs of the PWM generator immediately become the inputs to the dead time and output circuitry 1 PWM outputs controlled manually 0 PWM outputs determined by...

Page 155: ...e Figure 12 47 PWM cycle or period Center aligned mode The time it takes the PWM counter to count up and count down modulus 2 fOP assuming no prescaler See Figure 12 47 Edge aligned mode The time it t...

Page 156: ...PWM Load Frequency Frequency at which new PWM parameters get loaded into the PWM See Figure 12 48 Figure 12 48 PWM Load Cycle Frequency Definition RELOAD NEW MODULUS PRESCALER PWM VALUES IF LDOK 1 REL...

Page 157: ...k space non return to zero NRZ format 32 programmable baud rates Programmable 8 bit or 9 bit character length Separately enabled transmitter and receiver Separate receiver and transmitter CPU interrup...

Page 158: ...PTA DDRA DDRB PTB DDRC PTC PTD DDRE PTE PTF DDRF INTERNAL BUS OSC1 OSC2 CGMXFC RST IRQ VSS VDD VDDAD PTA7 PTA0 PTE7 TCH3A PTE6 TCH2A PTE5 TCH1A PTE4 TCH0A PTE3 TCLKA PTE2 TCH1B 1 PTE1 TCH0B 1 PTE0 TCL...

Page 159: ...operation the CPU monitors the status of the SCI writes the data to be transmitted and processes received data Figure 13 2 SCI Module Block Diagram SCTE TC SCRF IDLE OR NF FE PE SCTIE TCIE SCRIE ILIE...

Page 160: ...0 0 0 0 0 0 003B SCI Status Register 1 SCS1 See page 174 Read SCTE TC SCRF IDLE OR NF FE PE Write R R R R R R R R Reset 1 1 0 0 0 0 0 0 003C SCI Status Register 2 SCS2 See page 176 Read 0 0 0 0 0 0 B...

Page 161: ...ransmitter PEN PTY H 8 7 6 5 4 3 2 1 0 L 11 BIT TRANSMIT STOP START T8 SCTE SCTIE TCIE SBK TC f OP PARITY GENERATION MSB SCI DATA REGISTER LOAD FROM SCDR SHIFT ENABLE PREAMBLE ALL 1s BREAK ALL 0s TRAN...

Page 162: ...1 becomes set when the SCDR transfers a byte to the transmit shift register The SCTE bit indicates that the SCDR can accept new data from the internal data bus If the SCI transmit interrupt enable bit...

Page 163: ...le character return the TE bit to 1 before the stop bit of the current character shifts out to the PTF5 TxD pin Setting TE after the stop bit appears on PTF5 TxD causes data previously written to the...

Page 164: ...ta bit R8 in SCI control register 2 SCC2 is the ninth bit bit 8 When receiving 8 bit data bit R8 is a copy of the eighth bit bit 7 ALL 1s ALL 0s M WAKE ILTY PEN PTY BKF RPF H 8 7 6 5 4 3 2 1 0 L 11 BI...

Page 165: ...gnal with a frequency 16 times the baud rate To adjust for baud rate mismatch the RT clock is resynchronized at these times see Figure 13 7 After every start bit After the receiver detects a data bit...

Page 166: ...a successful start bit verification the noise flag NF is set and the receiver assumes that the bit is a start bit To verify a stop bit and to detect noise recovery logic takes samples at RT8 RT9 and...

Page 167: ...he standby state Idle input line condition When the WAKE bit is clear an idle character on the PTF4 RxD pin wakes the receiver from the standby state by clearing the RWU bit The idle character that wa...

Page 168: ...executing the WAIT instruction 13 5 SCI During Break Module Interrupts The system integration module SIM controls whether status bits in other modules can be cleared during interrupts generated by th...

Page 169: ...er SCDR SCI baud rate register SCBR 13 7 1 SCI Control Register 1 SCI control register 1 SCC1 Enables loop mode operation Enables the SCI Controls output polarity Controls character length Controls SC...

Page 170: ...it MSB position of a received character or an idle condition on the PTF4 RxD pin Reset clears the WAKE bit 1 Address mark wakeup 0 Idle line wakeup ILTY Idle Line Type Bit This read write bit determin...

Page 171: ...uests Setting the SCTIE bit in SCC3 enables SCTE CPU interrupt requests Reset clears the SCTIE bit 1 SCTE enabled to generate CPU interrupt 0 SCTE not enabled to generate CPU interrupt TCIE Transmissi...

Page 172: ...it 1 Transmitter enabled 0 Transmitter disabled NOTE Writing to the TE bit is not allowed when the enable SCI bit ENSCI is clear ENSCI is in SCI control register 1 RE Receiver Enable Bit Setting this...

Page 173: ...pt Enable Bit This read write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit OR 1 SCI error CPU interrupt requests from OR bit enabled 0 SCI error CPU interrupt req...

Page 174: ...ransmission Complete Bit This read only bit is set when the SCTE bit is set and no data preamble or break character is being transmitted TC generates an SCI transmitter CPU interrupt request if the TC...

Page 175: ...the ORIE bit in SCC3 is also set The data in the shift register is lost but the data already in the SCDR is not affected Clear the OR bit by reading SCS1 with OR set and then reading the SCDR Reset cl...

Page 176: ...r detected PE Receiver Parity Error Bit This clearable read only bit is set when the SCI detects a parity error in incoming data PE generates a PE CPU interrupt request if the PEIE bit in SCC3 is also...

Page 177: ...effect on data in the SCI data register R7 T7 R0 T0 Receive Transmit Data Bits Reading address 003D accesses the read only received data bits R7 R0 Writing to address 003D writes the data to be transm...

Page 178: ...SCR0 Use this formula to calculate the SCI baud rate where fOP internal operating frequency PD prescaler divisor BD baud rate divisor Table 13 7 shows the SCI baud rates that can be generated with a...

Page 179: ...00 1 110 64 1800 1200 00 1 111 128 900 600 01 3 000 1 38 400 25 600 01 3 001 2 19 200 12 800 01 3 010 4 9600 6400 01 3 011 8 4800 3200 01 3 100 16 2400 1600 01 3 101 32 1200 800 01 3 110 64 600 400 01...

Page 180: ...Serial Communications Interface Module SCI MC68HC908MR32 MC68HC908MR16 Data Sheet Rev 6 1 180 Freescale Semiconductor...

Page 181: ...ck control Master reset control including power on reset POR and computer operating properly COP timeout Interrupt control Acknowledge timing Arbitration control timing Vector address generation CPU e...

Page 182: ...er 4 Clock Generator Module CGM 14 2 2 Clock Startup from POR or LVI Reset When the power on reset POR module or the low voltage inhibit LVI module generates a reset the clocks to the CPU and peripher...

Page 183: ...F FEFE FEFF in monitor mode and assert the internal reset signal IRST IRST causes all registers to be returned to their default values and all modules to be returned to their reset states An internal...

Page 184: ...nternal Reset NOTE For LVI or POR resets the SIM cycles through 4096 CGMXCLK cycles during which the SIM forces the RST pin low The internal reset signal then follows the sequence from the falling edg...

Page 185: ...SIM reset status register SRSR is set and all other bits in the register are cleared 14 3 2 2 Computer Operating Properly COP Reset An input to the SIM is reserved for the COP reset signal The overfl...

Page 186: ...he low voltage inhibit LVI module asserts its output to the SIM when the VDD voltage falls to the VLVRX voltage and remains at or below that level for at least nine consecutive CPU cycles see 19 5 DC...

Page 187: ...pt RTI instruction recovers the CPU register contents from the stack so that normal processing can resume Figure 14 7 shows interrupt entry timing Figure 14 9 shows interrupt recovery timing Figure 14...

Page 188: ...8 Interrupt Processing NO NO YES AS MANY INTERRUPTS AS EXIST ON CHIP SWI INSTRUCTION RTI INSTRUCTION FETCH NEXT INSTRUCTION UNSTACK CPU REGISTERS STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT V...

Page 189: ...ates what happens when two interrupts are pending If an interrupt is pending upon exit from the original interrupt service routine the pending interrupt is serviced before the load accumulator from me...

Page 190: ...it mode entry A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled Stacking for the interrupt begins one cycle after the WAIT instruction during w...

Page 191: ...outputs will stop toggling when stop mode is entered The PWM module must be disabled before entering stop mode to prevent external inverter failure 14 7 SIM Registers This subsection describes the SI...

Page 192: ...Bit 1 Last reset caused by external reset pin RST 0 POR or read of SRSR COP Computer Operating Properly Reset Bit 1 Last reset caused by COP counter 0 POR or read of SRSR ILOP Illegal Opcode Reset Bi...

Page 193: ...ak state BCFE Break Clear Flag Enable Bit This read write bit enables software to clear status bits by accessing status registers while the MCU is in a break state To clear status bits during the brea...

Page 194: ...System Integration Module SIM MC68HC908MR32 MC68HC908MR16 Data Sheet Rev 6 1 194 Freescale Semiconductor...

Page 195: ...cessor unit CPU service SPRF SPI receiver full SPTE SPI transmitter empty Mode fault error flag with CPU interrupt capability Overflow error flag with CPU interrupt capability Programmable wired OR mo...

Page 196: ...A DDRA DDRB PTB DDRC PTC PTD DDRE PTE PTF DDRF INTERNAL BUS OSC1 OSC2 CGMXFC RST IRQ VSS VDD VDDAD PTA7 PTA0 PTE7 TCH3A PTE6 TCH2A PTE5 TCH1A PTE4 TCH0A PTE3 TCLKA PTE2 TCH1B 1 PTE1 TCH0B 1 PTE0 TCLKB...

Page 197: ...l devices including other MCUs Software can poll the SPI status flags or SPI operation can be interrupt driven All SPI interrupts can be serviced by the CPU Figure 15 2 SPI Module Block Diagram TRANSM...

Page 198: ...etermine the speed of the shift register See 15 12 2 SPI Status and Control Register Through the SPSCK pin the baud rate generator of the master also controls the shift register of the slave periphera...

Page 199: ...the data in the slave shift register begins shifting out on the MISO pin The slave can load its shift register with a new byte for the next transmission by writing to its transmit data register The s...

Page 200: ...nected between the master and the slave The MISO signal is the output from the slave and the MOSI signal is the output from the master The SS line is the slave select input to the slave The slave SPI...

Page 201: ...t shown but is assumed to be inactive The SS pin of the master must be high or must be reconfigured as general purpose I O not affecting the SPI See 15 6 2 Mode Fault Error When CPHA 1 the master begi...

Page 202: ...R occurs relative to the slower SPSCK This uncertainty causes the variation in the initiation delay shown in Figure 15 8 This delay is no longer than a single SPI bit time That is the maximum delay is...

Page 203: ...ear the overflow flag by reading the SPI status and control register and then reading the SPI data register OVRF generates a receiver error CPU interrupt request if the error interrupt enable bit ERRI...

Page 204: ...R To prevent SPI pin contention and damage to the MCU a mode fault error occurs if The SS pin of a slave SPI goes high during a transmission The SS pin of a master SPI goes low at any time For the MOD...

Page 205: ...until the SPSCK returns to its idle level following the shift of the last data bit See 15 5 Transmission Formats NOTE Setting the MODF flag does not clear the SPMSTR bit Reading SPMSTR when MODF 1 wi...

Page 206: ...e receiver error CPU interrupt requests These sources in the SPI status and control register can generate CPU interrupt requests SPI receiver full bit SPRF The SPRF bit becomes set every time a byte t...

Page 207: ...set 15 9 Queuing Transmission Data The double buffered transmit data register allows a data byte to be queued and transmitted For an SPI configured as a master a queued data byte is transmitted immed...

Page 208: ...e to the SPDR in break mode with the BCFE bit cleared has no effect 15 11 I O Signals The SPI module has five I O pins and shares four of them with a parallel I O port The pins are MISO Data received...

Page 209: ...is one of the two SPI module pins that transmits serial data In full duplex operation the MOSI pin of the master SPI module is connected to the MOSI pin of the slave SPI module The master SPI simulta...

Page 210: ...input only pin to the SPI regardless of the state of the data direction register of the shared I O port The CPU can always read the state of the SS pin by configuring the appropriate pin as an input a...

Page 211: ...sets the CPHA bit When CPHA 0 for a slave the falling edge of SS indicates the beginning of the transmission This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of...

Page 212: ...data register empty The SPI status and control register also contains bits that perform these functions Enable error interrupts Enable mode fault error detection Select master SPI baud rate SPRF SPI R...

Page 213: ...r an idle master of idle slave that has no data loaded into its transmit buffer the SPTE will be set again within two bus cycles since the transmit buffer empties into the shift register This allows t...

Page 214: ...egister Reading the SPI data register reads data from the receive data register The transmit data and receive data registers are separate registers that can contain different values See Figure 15 2 R7...

Page 215: ...a block diagram of the TIMA 16 2 Features Features of the TIMA include Four input capture output compare channels Rising edge falling edge or any edge input capture trigger Set clear or toggle output...

Page 216: ...DDRB PTB DDRC PTC PTD DDRE PTE PTF DDRF INTERNAL BUS OSC1 OSC2 CGMXFC RST IRQ VSS VDD VDDAD PTA7 PTA0 PTE7 TCH3A PTE6 TCH2A PTE5 TCH1A PTE4 TCH0A PTE3 TCLKA PTE2 TCH1B 1 PTE1 TCH0B 1 PTE0 TCLKB 1 PTF5...

Page 217: ...TSTOP TOV0 CH0IE CH0F CH0MAX MS0B 16 BIT COUNTER BUS CLOCK PTE4 TCH0A PTE5 TCH1A PTE6 TCH2A PTE7 TCH3A LOGIC RUPT LOGIC INTER RUPT LOGIC 16 BIT COMPARATOR 16 BIT LATCH TCH1H TCH1L MS1A ELS1B ELS1A PTE...

Page 218: ...t 1 1 1 1 1 1 1 1 0013 TIMA Channel 0 Status Control Register TASC0 See page 229 Read CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX Write 0 Reset 0 0 0 0 0 0 0 0 0014 TIMA Channel 0 Register High TACH0...

Page 219: ...hree basic parts 1 Edge select logic 2 Input capture latch 3 16 bit counter Two 8 bit registers which make up the 16 bit input capture register are used to latch the value of the free running counter...

Page 220: ...erence In this case an input capture function is used in conjunction with an output compare function For example to activate an output signal a specified number of clock cycles after detecting an inpu...

Page 221: ...TASC1 is unused While the MS0B bit is set the channel 1 pin PTE5 TCH1A is available as a general purpose I O pin Channels 2 and 3 can be linked to form a buffered output compare channel whose output...

Page 222: ...nel registers to change a pulse width value could cause incorrect operation for up to two PWM periods For example writing a new value before the counter reaches the old value but after the counter rea...

Page 223: ...channel registers of the linked pair alternately control the pulse width of the output Setting the MS2B bit in TIMA channel 2 status and control register TASC2 links channel 2 and channel 3 The TIMA...

Page 224: ...ter 0 TASC0 controls and monitors the PWM signal from the linked channels MS0B takes priority over MS0A Setting MS2B links channels 2 and 3 and configures them for buffered PWM operation The TIMA chan...

Page 225: ...d Control Register The maximum TCLK frequency is the least 4 MHz or bus frequency 2 PTE3 TCLKA is available as a general purpose I O pin when not used as the TIMA clock input When the PTE3 TCLKA pin i...

Page 226: ...nterrupts disabled TSTOP TIMA Stop Bit This read write bit stops the TIMA counter Counting resumes when TSTOP is cleared Reset sets the TSTOP bit stopping the TIMA counter until software clears the TS...

Page 227: ...TRST also clears the TIMA counter registers NOTE If TACNTH is read during a break interrupt be sure to unlatch TACNTL by reading TACNTL before exiting the break interrupt Otherwise TACNTL retains the...

Page 228: ...Registers Each of the TIMA channel status and control registers Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture output compare or PW...

Page 229: ...ffect 1 Input capture or output compare on channel x 0 No input capture or output compare on channel x CHxIE Channel x Interrupt Enable Bit This read write bit enables TIMA CPU interrupts on channel x...

Page 230: ...CHxA pin once PWM input capture or output compare operation is enabled See Table 16 2 Reset clears the MSxA bit 1 Initial output level low 0 Initial output level high NOTE Before changing a channel fu...

Page 231: ...o 100 percent As Figure 16 9 shows CHxMAX bit takes effect in the cycle after it is set or cleared The output stays at 100 percent duty cycle level until the cycle after CHxMAX is cleared Figure 16 9...

Page 232: ...xL is written Register Name and Address TACH0H 0014 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset Indeterminate after reset Register Name and Address T...

Page 233: ...Reset Indeterminate after reset Register Name and Address TACH3H 001D Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset Indeterminate after reset Register...

Page 234: ...Timer Interface A TIMA MC68HC908MR32 MC68HC908MR16 Data Sheet Rev 6 1 234 Freescale Semiconductor...

Page 235: ...generation Programmable TIMB clock input 7 frequency internal bus clock prescaler selection External TIMB clock input 4 MHz maximum frequency Free running or modulo up count operation Toggle any chan...

Page 236: ...DDRB PTB DDRC PTC PTD DDRE PTE PTF DDRF INTERNAL BUS OSC1 OSC2 CGMXFC RST IRQ VSS VDD VDDAD PTA7 PTA0 PTE7 TCH3A PTE6 TCH2A PTE5 TCH1A PTE4 TCH0A PTE3 TCLKA PTE2 TCH1B 1 PTE1 TCH0B 1 PTE0 TCLKB 1 PTF5...

Page 237: ...eset 0 0 0 0 0 0 0 0 0054 TIMB Counter Modulo Register High TBMODH See page 246 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reset 1 1 1 1 1 1 1 1 0055 TIMB Counter Modulo Register...

Page 238: ...es can generate TIMB CPU interrupt requests Software can determine that an input capture event has occurred by enabling input capture interrupts or by polling the status flag bit The free running coun...

Page 239: ...er TBCHxH TBCHxL 17 3 3 Output Compare With the output compare function the TIMB can generate a periodic pulse with a programmable polarity duration and frequency When the counter reaches the value in...

Page 240: ...active channel Writing to the active channel registers is the same as generating unbuffered output compares 17 3 4 Pulse Width Modulation PWM By using the toggle on overflow feature with an output co...

Page 241: ...ble TIMB overflow interrupts and write the new value in the TIMB overflow interrupt routine The TIMB overflow interrupt occurs at the end of the current PWM period Writing a larger value in an output...

Page 242: ...pare to the edge level select bits ELSxB ELSxA The output action on compare must force the output to the complement of the pulse width level See Table 17 2 NOTE In PWM signal generation do not program...

Page 243: ...functions are not required during wait mode reduce power consumption by stopping the TIMB before executing the WAIT instruction 17 6 I O Signals Port E shares three of its pins with the TIMB PTE0 TCL...

Page 244: ...the modulo value programmed in the TIMB counter modulo registers Clear TOF by reading the TIMB status and control register when TOF is set and then writing a logic 0 to TOF If another TIMB overflow oc...

Page 245: ...B counter and the TIMB prescaler Setting TRST has no effect on any other registers Counting resumes from 0000 TRST is cleared automatically after the TIMB counter is reset and always reads as logic 0...

Page 246: ...erflow flag TOF becomes set and the TIMB counter resumes counting from 0000 at the next timer clock Writing to the high byte TBMODH inhibits the TOF bit and overflow interrupts until the low byte TBMO...

Page 247: ...ue in the TIMB channel x registers When CHxIE 1 clear CHxF by reading TIMB channel x status and control register with CHxF set and then writing a 0 to CHxF If another interrupt request occurs before t...

Page 248: ...T bits in the TIMB status and control register TBSC ELSxB and ELSxA Edge Level Select Bits When channel x is an input capture channel these read write bits control the active edge sensing logic on cha...

Page 249: ...leared Figure 17 9 CHxMAX Latency Table 17 2 Mode Edge and Level Selection MSxB MSxA ELSxB ELSxA Mode Configuration X0 00 Output preset Pin under port control initialize timer output level high X1 00...

Page 250: ...TIMB channel x registers TBCHxH inhibits output compares until the low byte TBCHxL is written Register Name and Address TBCH0H 0057 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit...

Page 251: ...to the CPU The CPU then loads the instruction register with a software interrupt instruction SWI after completion of the current CPU instruction The program counter vectors to FFFC and FFFD FEFC and F...

Page 252: ...FE0C Break Address Register High BRKH See page 254 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 FE0D Break Address Register Low BRKL See page 254 Read Bit 7 6 5 4 3 2 1 Bit 0 Write...

Page 253: ...reak Interrupts The COP is disabled during a break interrupt when VTST is present on the RST pin 18 2 2 Low Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby mode...

Page 254: ...a break interrupt Clear BRKA by writing a logic 0 to it before exiting the break routine Reset clears the BRKA bit 1 When read break address match 0 When read no break address match 18 2 3 2 Break Ad...

Page 255: ...bit that enables software to clear status bits while the MCU is in a break state BCFE Break Clear Flag Enable Bit This read write bit enables software to clear status bits by accessing status registe...

Page 256: ...re two methods for entering monitor The first is the traditional M68HC08 method where VDD VHI is applied to IRQ1 and the mode pins are configured appropriately A second method intended for in circuit...

Page 257: ...F 10 k 6 5 2 4 3 1 DB 25 2 3 7 20 18 17 19 16 15 VDD VDD VDD 20 pF 20 pF 10 F 10 F 10 F 10 F 1 2 4 7 14 3 0 1 F 4 9152 MHz 10 k PTC2 VDD 10 k B A S2 Position A Bus clock CGMXCLK 4 or CGMVCLK 4 S2 Pos...

Page 258: ...urity code entry X GND X X X X X X 0 0 Disabled X X 0 No operation until reset goes high VTST VDD or VTST X OFF 1 0 0 4 9152 MHz 4 9152 MHz 2 4576 MHz Disabled 1 0 9600 PTC3 and PTC2 voltages only req...

Page 259: ...modes of operation 18 3 1 3 Forced Monitor Mode If the voltage applied to the IRQ1 is less than VDD VHI the MCU will come out of reset in user mode The MENRST module is monitoring the reset vector fe...

Page 260: ...d by nine low bits is a break signal See Figure 18 12 When the monitor receives a break signal it drives the PTA0 pin high for the duration of two bits before echoing the break signal Figure 18 12 Bre...

Page 261: ...e address in high byte low byte order low byte followed by data byte Data Returned None Opcode 49 Command Sequence Table 18 5 IREAD Indexed Read Command Description Read next 2 bytes in memory from la...

Page 262: ...byte Data Returned None Opcode 19 Command Sequence Table 18 7 READSP Read Stack Pointer Command Description Reads stack pointer Operand None Data Returned Returns incremented stack pointer value SP 1...

Page 263: ...ty remains bypassed and security code entry is not required See Figure 18 13 Upon power on reset if the received bytes of the security code do not match the data at locations FFF6 FFFD the host fails...

Page 264: ...Mode Entry Timing BYTE 1 BYTE 1 ECHO BYTE 2 BYTE 2 ECHO BYTE 8 BYTE 8 ECHO COMMAND COMMAND ECHO PA0 PA7 RST VDD 4096 32 CGMXCLK CYCLES 24 BUS CYCLES 256 BUS CYCLES MINIMUM 1 3 1 1 2 1 BREAK NOTES 2 Da...

Page 265: ...high static voltages or electric fields however it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit For...

Page 266: ...nge 40 C to 105 C TA 40 to 85 40 to 105 C Operating voltage range VDD 5 0 10 V Characteristic Symbol Value Unit Thermal resistance 64 pin QFP JA 76 C W I O pin power dissipation PI O User determined W...

Page 267: ...pF on all outputs CL 20 pF on OSC2 all ports configured as inputs OSC2 capacitance linearly affects wait IDD measured with PLL and LVI enabled 5 Stop IDD measured with PLL and LVI disengaged OCS1 grou...

Page 268: ...ndition tNVS tNVH tPGS tPROG x 32 tHV maximum 4 ms FLASH endurance 4 4 Typical endurance was evaluated for this product family For additional information on how Freescale defines Typical Endurance ple...

Page 269: ...P 128 dc fOP 2 fOP MHz 1 Cycle time Master Slave tCYC M tCYC S 2 1 128 tCYC 2 Enable lead time tLead S 15 ns 3 Enable lag time tLag S 15 ns 4 Clock SPCK high time Master Slave tSCKH M tSCKH S 100 50 n...

Page 270: ...N MASTER MSB OUT BITS 6 1 MASTER LSB OUT 10 11 10 11 7 6 NOTE Note This last clock edge is generated internally but is not seen at the SCK pin SS PIN OF MASTER HELD HIGH MSB IN SS INPUT SPCK CPOL 0 OU...

Page 271: ...OL 0 INPUT SPCK CPOL 1 INPUT MISO INPUT MOSI OUTPUT 4 5 5 1 4 MSB IN BITS 6 1 8 6 10 11 11 NOTE SLAVE LSB OUT 9 3 LSB IN 2 7 BITS 6 1 MSB OUT Note Not defined but normally LSB of character previously...

Page 272: ...fixed capacitance C1 2 CL Consult crystal manufacturing data Crystal tuning capacitance C2 2 CL Consult crystal manufacturing data Feedback bias resistor RB 22 M Series resistor RS 0 330 k 1 M Not req...

Page 273: ...chosen correctly Manual acquisition time tLock tACQ tAL Tracking mode entry frequency tolerance TRK 0 3 6 Acquisition mode entry frequency tolerance ACQ 6 3 7 2 Lock entry frequency tolerance Lock 0...

Page 274: ...s Absolute accuracy AAD 4 LSB Includes quantization ADC internal clock fADIC 500 k 1 048 M Hz tAIC 1 fADIC Conversion range RAD VSSAD VDDAD V Power up time tADPU 16 tAIC cycles Conversion time tADC 16...

Page 275: ...time of this publication To make sure that you have the latest package specifications contact your local Freescale Sales Office 20 2 Order Numbers Figure 20 1 Device Numbering System Table 20 1 Order...

Page 276: ...Ordering Information and Mechanical Specifications MC68HC908MR32 MC68HC908MR16 Data Sheet Rev 6 1 276 Freescale Semiconductor 20 3 64 Pin Plastic Quad Flat Pack QFP...

Page 277: ...56 Pin Shrink Dual In Line Package SDIP MC68HC908MR32 MC68HC908MR16 Data Sheet Rev 6 1 Freescale Semiconductor 277 20 4 56 Pin Shrink Dual In Line Package SDIP...

Page 278: ...Ordering Information and Mechanical Specifications MC68HC908MR32 MC68HC908MR16 Data Sheet Rev 6 1 278 Freescale Semiconductor...

Page 279: ...R32 MC68HC908MR16 Data Sheet Rev 6 1 Freescale Semiconductor 279 Appendix A MC68HC908MR16 The information contained in this document pertains to the MC68HC908MR16 with the exception of that shown in F...

Page 280: ...K FLAG CONTROL REGISTER SBFCR FE04 RESERVED FE05 RESERVED FE06 RESERVED FE07 RESERVED FE08 FLASH CONTROL REGISTER FLCR FE09 UNIMPLEMENTED FE0A UNIMPLEMENTED FE0B UNIMPLEMENTED FE0C SIM BREAK ADDRESS R...

Page 281: ......

Page 282: ...articular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including witho...

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