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MC68332

REGISTER SUMMARY

USER’S MANUAL

D-17

RAMDS — RAM Array disabled

0 = RAM array is enabled

1 = RAM array is disabled

The TPURAM array is disabled by internal logic after a master reset. Writing a valid

base address to the RAM array base address field (bits [15:3]) automatically clears

RAMDS, enabling the RAM array.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

Summary of Contents for MC68332

Page 1: ...The content and copyrights of the attached material are the property of its owner Distributed by www Jameco com 1 800 831 4242 Jameco Part Number 961012UsersManual...

Page 2: ...NC 1995 M68300 Family MC68332 User s Manual Freescale Semiconductor I For More Information On This Product Go to www freescale com nc Freescale Semiconductor Freescale Semiconductor Inc 2004 All right...

Page 3: ...ilure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or...

Page 4: ...Descriptions 3 5 3 4 Signal Descriptions 3 7 3 5 Intermodule Bus 3 9 3 6 System Memory Map 3 9 3 6 1 Internal Register Map 3 10 3 6 2 Address Space Maps 3 10 3 7 System Reset 3 15 3 7 1 SIM Reset Mode...

Page 5: ...s 4 19 4 4 1 8 Data and Size Acknowledge Signals 4 19 4 4 1 9 Bus Error Signal 4 20 4 4 1 10 Halt Signal 4 20 4 4 1 11 Autovector Signal 4 20 4 4 2 Dynamic Bus Sizing 4 20 4 4 3 Operand Alignment 4 21...

Page 6: ...upts 4 46 4 7 1 Interrupt Exception Processing 4 46 4 7 2 Interrupt Priority and Recognition 4 46 4 7 3 Interrupt Acknowledge and Arbitration 4 47 4 7 4 Interrupt Processing Summary 4 48 4 7 5 Interru...

Page 7: ...ocessing 5 13 5 9 1 Exception Vectors 5 13 5 9 2 Types of Exceptions 5 14 5 9 3 Exception Processing Sequence 5 15 5 10 Development Support 5 15 5 10 1 M68000 Family Development Support 5 15 5 10 2 Ba...

Page 8: ...lave Mode 6 20 6 3 5 4 Slave Wraparound Mode 6 22 6 3 6 Peripheral Chip Selects 6 22 6 4 Serial Communication Interface 6 22 6 4 1 SCI Registers 6 22 6 4 1 1 Control Registers 6 22 6 4 1 2 Status Regi...

Page 9: ...4 7 Period Measurement with Missing Transition Detect PMM 7 7 7 4 8 Position Synchronized Pulse Generator PSP 7 7 7 4 9 Stepper Motor SM 7 8 7 4 10 Period Pulse Width Accumulator PPWA 7 8 7 4 11 Quad...

Page 10: ...ration 8 3 8 8 Reset 8 3 8 9 TPU Microcode Emulation 8 3 APPENDIX A ELECTRICAL CHARACTERISTICS APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION APPENDIX CDEVELOPMENT SUPPORT C 1 M68MMDS1632 Modular...

Page 11: ...nt Register 1 YFFA46 D 13 D 2 25 CSBARBT Chip Select Base Address Register Boot ROM YFFA48 D 13 D 2 26 CSBAR 0 10 Chip Select Base Address Registers YFFA4C YFFA74 D 13 D 2 27 CSORBT Chip Select Option...

Page 12: ...nterrupt Enable Register YFFE0A D 34 D 5 7 CFSR0 Channel Function Select Register 0 YFFE0C D 34 D 5 8 CFSR1 Channel Function Select Register 1 YFFE0E D 34 D 5 9 CFSR2 Channel Function Select Register...

Page 13: ...MC68332 USER S MANUAL Continued Paragraph Title Page TABLE OF CONTENTS Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 14: ...ing 4 27 4 12 Breakpoint Operation Flowchart 4 30 4 13 LPSTOP Interrupt Mask Level 4 31 4 14 Bus Arbitration Flowchart for Single Request 4 36 4 15 Data Bus Mode Select Conditioning 4 40 4 16 Power On...

Page 15: ...d Cycle Timing Diagram A 17 A 7 Fast Termination Write Cycle Timing Diagram A 18 A 8 Bus Arbitration Timing Diagram Active Bus Case A 19 A 9 Bus Arbitration Timing Diagram Idle Bus Case A 20 A 10 Show...

Page 16: ...ases 4 22 4 14 DSACK BERR and HALT Assertion Results 4 32 4 15 Reset Source Summary 4 38 4 16 Reset Mode Selection 4 39 4 17 Module Pin Functions 4 42 4 18 SIM Pin Reset States 4 43 4 19 Chip Select P...

Page 17: ...A 6 16 78 MHz AC Timing A 9 A 6 a 20 97 MHz AC Timing A 11 A 7 Background Debugging Mode Timing A 22 A 8 16 78 MHz ECLK Bus Timing A 24 A 8 a 20 97 MHz ECLK Bus Timing A 24 A 9 QSPI Timing A 26 A 10 1...

Page 18: ...tion Because MCU operation is fully static register and memory contents are not af fected by clock rate changes High density complementary metal oxide semiconductor HCMOS architecture makes the basic...

Page 19: ...INTRODUCTION MC68332 1 2 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 20: ...Operators Addition Subtraction or negation two s complement Multiplication Division Greater Less Equal Equal or greater Equal or less Not equal AND Inclusive OR OR Exclusive OR EOR NOT Complementation...

Page 21: ...0 Data Registers Index registers DFC Alternate function code register PC Program counter SFC Alternate function code register SR Status register VBR Vector base register X Extend indicator N Negative...

Page 22: ...ze HALT Halt IFETCH Instruction Fetch IPIPE Instruction Pipeline IRQ 7 1 Interrupt Request MISO Master In Slave Out MODCLK Clock Mode Select MOSI Master Out Slave In PC 6 0 SIM I O Port C PCS 3 0 Peri...

Page 23: ...0 1 Host Sequence Registers 0 1 HSRR 0 1 Host Service Request Registers 0 1 LR Link Register PEPAR Port E Pin Assignment Register PFPAR Port F Pin Assignment Register PICR Periodic Interrupt Control R...

Page 24: ...cumulator M CSOR 0 5 are the first six option registers Parentheses are used to indicate the content of a register or memory location rather than the register or memory location itself A is the conten...

Page 25: ...NOMENCLATURE MC68332 2 6 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 26: ...ort Programmable Chip Select Outputs System Protection Logic Watchdog Timer Clock Monitor and Bus Monitor System Protection Logic System Clock Based on 32 768 kHz Crystal for Low Power Operation Test...

Page 27: ...l diagram of the MCU Although diagram blocks represent the relative size of the physical modules there is not a one to one correspondence be tween location and size of blocks in the diagram and locati...

Page 28: ...T BERR CLKOUT XTAL EXTAL CHIP SELECTS CSBOOT ADDR 18 0 DATA 15 0 DATA 15 0 QUOT TEST FREEZE QUOT TSC CONTROL TSC PC0 FC0 CS3 PC1 FC1 CS4 PC2 FC2 CS5 PC3 ADDR19 CS6 PC4 ADDR20 CS7 PC5 ADDR21 CS8 PC6 AD...

Page 29: ...G CS1 BR CS0 VSTBY 51 17 117 16 15 14 13 12 11 10 9 8 7 6 5 4 3 131 130 129 128 127 126 125 124 123 122 121 120 119 118 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78...

Page 30: ...TCH DSI IPIPE DSO RXD PQS7 TXD VSS NC TPUCH3 TPUCH2 TPUCH1 TPUCH0 NC 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 107 108 106 105 104 103 102 101 100 99 98 97 96 95...

Page 31: ...put Hysteresis Discrete I O Port Designation ADDR23 CS10 ECLK A Y N O ADDR 22 19 CS 9 6 A Y N O PC 6 3 ADDR 18 0 A Y N AS B Y N I O PE5 AVEC B Y N I O PE2 BERR B Y N BG CS1 B BGACK CS2 B Y N BKPT DSCL...

Page 32: ...VDDE External Periphery Power Source and Drain VSSI VDDI Internal Module Power Source and Drain Table 3 4 MCU Signal Characteristics Signal Name MCU Module Signal Type Active State ADDR 23 0 SIM Bus A...

Page 33: ...ACK Indicates that an external device has assumed bus mastership Breakpoint BKPT Signals a hardware breakpoint to the CPU Bus Request BR Indicates that an external device requires bus mastership Syste...

Page 34: ...ster mode serial input to QSPI in slave mode Port C PC 6 0 SIM digital output port signals Auxiliary Timer Clock Input PCLK External clock dedicated to the GPT Peripheral Chip Select PCS 3 0 QSPI peri...

Page 35: ...resulting in four separate memory spaces supervisor program supervisor data user program and user data All exception vectors are located in supervisor data space except the reset vector which is loca...

Page 36: ...CE LINE 1010 EMULATOR LINE 1111 EMULATOR HARDWARE BREAKPOINT RESERVED COPROCESSOR PROTOCOL VIOLATION FORMAT ERROR AND UNINITIALIZED INTERRUPT FORMAT ERROR AND UNINITIALIZED INTERRUPT UNASSIGNED RESERV...

Page 37: ...ROCESSOR PROTOCOL VIOLATION FORMAT ERROR AND UNINITIALIZED INTERRUPT FORMAT ERROR AND UNINITIALIZED INTERRUPT UNASSIGNED RESERVED SPURIOUS INTERRUPT LEVEL 1 INTERRUPT AUTOVECTOR LEVEL 2 INTERRUPT AUTO...

Page 38: ...NINITIALIZED INTERRUPT UNASSIGNED RESERVED SPURIOUS INTERRUPT LEVEL 1 INTERRUPT AUTOVECTOR LEVEL 2 INTERRUPT AUTOVECTOR LEVEL 3 INTERRUPT AUTOVECTOR LEVEL 4 INTERRUPT AUTOVECTOR LEVEL 5 INTERRUPT AUTO...

Page 39: ...of the vector base register and the vector offset 2 Unused addresses within the internal register block are mapped externally RESERVED blocks are not mapped externally YFF000 YFFA00 SIM YFFA80 RESERV...

Page 40: ...happens during subsequent breakpoint as sertions Table 3 6 is a summary of reset mode selection options Table 3 6 SIM Reset Mode Selection Mode Select Pin Default Function Pin Left High Alternate Func...

Page 41: ...al module sections in this manual for more infor mation Table 3 7 is a summary of module pin function out of reset Table 3 7 Module Pin Functions Module Pin Mnemonic Function CPU32 DSI IFETCH DSI IFET...

Page 42: ...critical control routines The system clock generates clock signals used by the SIM other IMB modules and external devices The external bus interface handles the transfer of information between IMB mo...

Page 43: ...rves reset status monitors internal activity and provides periodic interrupt generation Figure 4 2 is a block diagram of the submodule S C IM BLOCK SYSTEM CONFIGURATION AND PROTECTION CLOCK SYNTHESIZE...

Page 44: ...ses range from FFF000 to FFFFFF 4 2 2 Interrupt Arbitration Each module that can generate interrupt requests has an interrupt arbitration IARB field Arbitration between interrupt requests of the same...

Page 45: ...est Slave mode is enabled by holding DATA11 low during reset The slave enabled SLVEN bit is a read only bit that shows the reset state of DATA11 4 2 5 Register Access The CPU32 can operate at either o...

Page 46: ...bus Refer to 4 5 5 2 Double Bus Faults for more information Halt monitor reset can be inhibited by the halt monitor HME bit in SYPCR 4 2 9 Spurious Interrupt Monitor During interrupt exception process...

Page 47: ...ange SWP value The SWT field selects the divide ratio used to establish software watchdog time out period Time out period is given by the following equations or Table 4 4 shows the ratio for each comb...

Page 48: ...op tions either no prescaling or prescaling by a factor of 512 can be selected The value of PTP is affected by the state of the MODCLK pin during reset as shown in Table 4 5 System software can change...

Page 49: ...SIMCR and the MCU enters low power stop mode The bus monitor halt monitor and spurious interrupt monitor are all inactive during low power stop During low power stop the clock input to the software wa...

Page 50: ...the SIM provides timing signals for the IMB modules and for an external peripheral bus Because the MCU is a fully static design register and memory contents are not affected when the clock rate change...

Page 51: ...ed reference frequency External system clock signal frequency must be less than or equal to maximum specified system clock frequency When an external system clock signal is applied PLL disabled MODCLK...

Page 52: ...lock stability Figure 4 6 shows two recommended filters XFC pin leakage must be as specified in APPENDIX A ELECTRICAL CHARACTERISTICS to maintain optimum stability and PLL performance An external filt...

Page 53: ...X and Y bits must be within the limits specified for the MCU Do not use a com bination of bit values that selects either an operating frequency or a VCO frequency greater than the maximum specified va...

Page 54: ...0 180 360 720 1440 101101 184 368 736 1472 101110 188 376 752 1504 101111 192 384 768 1536 110000 196 392 784 1568 110001 200 400 800 1600 110010 204 408 816 1632 110011 208 416 832 1664 110100 212 42...

Page 55: ...456 8913 17826 010001 2359 4719 9437 18874 010010 2490 4981 9961 19923 010011 2621 5243 10486 20972 010100 2753 5505 11010 22020 010101 2884 5767 11534 23069 010110 3015 6029 12059 24117 010111 3146 6...

Page 56: ...executes LPSTOP a special CPU space bus cycle writes a copy of the current interrupt mask into the clock control logic The SIM brings the MCU out of low power operation when either an interrupt of hi...

Page 57: ...state out of reset the clock synthesizer is forced into an operating condition referred to as limp mode Limp mode frequency varies from device to device but maximum limp frequency does not exceed one...

Page 58: ...red during an access is referred to as port width Widths of eight and sixteen bits can be accessed by asynchronous bus cycles con trolled by the data size SIZ 1 0 and the data and size acknowledge DSA...

Page 59: ...s Signals DATA 15 0 form a bidirectional nonmultiplexed parallel bus that transfers data to or from the MCU A read or write operation can transfer eight or sixteen bits of data in one bus cycle During...

Page 60: ...supervisor or user mode Addressing mode and the instruction being executed deter mine whether a memory access is to program or data space 4 4 1 8 Data and Size Acknowledge Signals During normal bus t...

Page 61: ...is returned to the MCU the address function code size and read write signals are again driven to their previous states The MCU does not service interrupt requests while it is halted Refer to 4 5 5 Bu...

Page 62: ...ssed first while OP3 the least significant byte is accessed last The two bytes of a word length operand are OP0 most significant and OP1 The single byte of a byte length operand is OP0 Figure 4 8 Oper...

Page 63: ...r external bus cycles use handshaking between the MCU and external peripherals to manage transfer size and data These accesses take three system clock cycles again with no wait states During regular c...

Page 64: ...s Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for more information Bus cycles terminated by DSACK assertion normally require a minimum of three CLK OUT cycles To support systems that use CLKOUT to...

Page 65: ...response time exceeds a predetermined limit Bus monitor period is determined by the BMT field in SYPCR The bus monitor cannot be disabled maximum mon itor period is 64 system clock cycles If no periph...

Page 66: ...ligned Operands for more infor mation Figure 4 10 is a flowchart of a write cycle operation for a word transfer Refer to the SIM Reference Manual SIMRM AD for more information RD CYC FLOW MCU PERIPHER...

Page 67: ...o gram one DSACK field for fast termination and the remaining DSACK fields for exter nal termination Fast termination cycles use internal handshaking signals generated by the chip select logic To init...

Page 68: ...cles Function code signals FC 2 0 designate which of eight external address spaces is ac cessed during a bus cycle Address space 7 is designated CPU space CPU space is used for control information not...

Page 69: ...processing it acquires the number of the illegal instruction exception vector computes the vector address from this number loads the content of the vector address into the PC and jumps to the excepti...

Page 70: ...ed with an operand fetch exception processing occurs at the end of the instruc tion during which BKPT is latched Refer to the CPU32 Reference Manual CPU32RM AD and the SIM Reference Man ual SIMRM AD f...

Page 71: ...GATE AS AND DS 3 GO TO A IF BKPT PIN ASSERTED AND DSACK IS ASSERTED 1 NEGATE AS AND DS 2 GO TO A IF BERR ASSERTED 1 NEGATE AS AND DS 2 GO TO B A B 1 ASSERT BERR TO INITIATE EXCEPTION PROCESSING IF BKP...

Page 72: ...st write cycle Figure 4 13 LPSTOP Interrupt Mask Level 4 5 5 Bus Exception Control Cycles An external device or a chip select circuit must assert at least one of the DSACK 1 0 signals or the AVEC sign...

Page 73: ...HARACTERISTICS for timing requirements External circuitry that provides these signals must be designed with these constraints in mind or else the internal bus monitor must be used DSACK BERR and HALT...

Page 74: ...nal bus interface does not latch data when an external bus cycle is terminated by a bus error When this occurs during an in struction prefetch the IMB precharge state bus pulled high or FF is latched...

Page 75: ...the bus cycle again The MCU retries any read or write cycle of an indivisible read modify write operation separately RMC remains asserted during the entire retry sequence The MCU will not relinquish...

Page 76: ...s bus request signal BR B The MCU asserts the bus grant signal BG to indicate that the bus is available C An external device asserts the bus grant acknowledge BGACK signal to indi cate that it has ass...

Page 77: ...g re set In slave mode when BG is asserted the MCU is slaved to an external master that has full access to all internal registers 4 5 6 2 Show Cycles The MCU normally performs internal data transfers...

Page 78: ...ry from catastrophic failure The MCU performs resets with a combination of hardware and software The system integration module determines whether a reset is valid asserts control signals per forms bas...

Page 79: ...or synchronous resets When a bus cycle does not terminate normally the bus monitor terminates it Refer to Table 4 15 for a summary of reset sources Internal single byte or aligned word writes are guar...

Page 80: ...after RESET is re leased If external mode selection logic causes a conflict of this type an isolation re sistor on the driven lines may be required Figure 4 15 shows a recommended method for conditio...

Page 81: ...efer to 4 8 4 Chip Select Reset Operation for more information DATA1 and DATA2 determine the functions of CS 2 0 and CS 5 3 respectively DA TA 7 3 determine the functions of an associated chip select...

Page 82: ...ro when sampled an internal BDM flag is set and the CPU32 enters background debugging mode whenever either BKPT input is subsequently asserted If both BKPT inputs are at logic level one when sampled b...

Page 83: ...r inactive states After RESET is released mode selection occurs and reset exception processing begins Pins configured as inputs during reset become active high impedance loads after RESET is released...

Page 84: ...is no longer being externally driven to guarantee this length of reset to the entire system Table 4 18 SIM Pin Reset States State While Pin State After RESET Released Mnemonic RESET Asserted Pin Func...

Page 85: ...ameters and by oscillator circuit design VDD ramp up time also affects pin state dur ing reset Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for voltage and timing specifications During power on rese...

Page 86: ...et to 7 disabling all interrupts below priority 7 C The vector base register is initialized to 000000 The following events take place when MSTRST is negated after assertion A The CPU32 samples the BKP...

Page 87: ...00 This value can be changed by programming the vector base register VBR with a new val ue and multiple vector tables can be used Refer to SECTION 5 CENTRAL PRO CESSING UNIT for more information conce...

Page 88: ...uests of a priority higher than the interrupt priority mask value it places the interrupt request level on the address bus and initiates a CPU space read cycle The request level serves two purposes it...

Page 89: ...l If the device does not respond in time the EBI bus monitor asserts the bus error signal BERR and a spuri ous interrupt exception is taken Chip select logic can also be used to generate internal AVEC...

Page 90: ...als appropriate to the access The CPU acquires the vector number 3 The AVEC signal is asserted the signal can be asserted by the dominant interrupt source or the pin can be tied low and the CPU genera...

Page 91: ...p select function is given the same address as a microcontroller module or an internal memory array an access to that address goes to the module or array and the chip select sig nal is not asserted Th...

Page 92: ...tput Blocks of addresses are assigned to each chip select function Block sizes of two Kbytes to one Mbyte can be selected by writing values to the appropriate base address register CSBAR 0 10 CSBARBT...

Page 93: ...ction 11 or alternate function 01 can be select ed during reset All pins except the boot ROM select pin CSBOOT are disabled out of reset There are twelve chip select functions and only eight associate...

Page 94: ...n address within a block The value of the base address must be a multiple of block size Base address register diagrams show how base register bits correspond to address lines After reset the MCU fetch...

Page 95: ...serted synchronized with the address strobe Selecting data strobe causes a chip select signal to be asserted synchronized with the data strobe This bit has no effect in synchronous mode The DSACK fiel...

Page 96: ...W fields 4 ADDR0 and or SIZ bits to the BYTE field 16 bit ports only 5 Priority of the interrupt being acknowledged ADDR 3 1 to IPL fields when the access is an interrupt acknowledge cycle When a matc...

Page 97: ...e Perform the following operations before using a chip select to generate an interrupt ac knowledge signal 1 Program the base address field to all ones 2 Program block size to no more than 64 Kbytes s...

Page 98: ...ult out of reset The BYTE field in option register CSORBT has a reset value of both bytes so that the select signal is enabled out of reset The LSB value of the CSBOOT field determined by the logic le...

Page 99: ...A write to the port E and port F data registers PORTE and PORTF is stored in an internal data latch and if any pin in the corresponding port is configured as an output the value stored for that bit i...

Page 100: ...esources The data registers readily support 8 bit byte 16 bit word and 32 bit long word operand lengths for all operations Word and long word operations support address manipula tion Although the prog...

Page 101: ...the MC68010 and later processors The CPU32 has eight 32 bit data registers seven 32 bit address registers a 32 bit program counter separate 32 bit supervisor and user stack pointers a 16 bit status re...

Page 102: ...rs 8 bits Word Integers 16 bits Long Word Integers 32 bits Quad Word Integers 64 bits 31 16 15 8 7 0 D0 D1 D2 D3 DATA REGISTERS D4 D5 D6 D7 31 16 15 0 A0 A1 A2 A3 ADDRESS REGISTERS A4 A5 A6 31 16 15 0...

Page 103: ...igned Quad words may be organized in any two data registers without restrictions on order or pairing There are no explicit instructions for the management of this data type although the MOVEM instruct...

Page 104: ...ain control information for supervi sor functions and vary in size With the exception of the condition code register the user portion of the status register they are accessed only by instructions at t...

Page 105: ...d to transfer val ues to and from the alternate function code registers This is a long word transfer the upper 29 bits are read as zeros and are ignored when written 5 2 5 Vector Base Register VBR The...

Page 106: ...HIGH ORDER LOW ORDER MSB LSB 0 LSB MSB 15 MSD Most Significant Digit LSD Least Significant Digit DECIMAL DATA BCD DIGITS 1 BYTE 15 12 11 8 7 4 3 0 MSD BCD 0 BCD 4 BCD 1 BCD 5 BCD 2 BCD 6 BCD 3 BCD 7...

Page 107: ...s register oriented Most instructions allow the results of the specified operation to be placed either in a register or directly in memory There is no need for extra instructions to store register con...

Page 108: ...or stack pointer SSP is used for stack operations 5 8 Instructions The CPU32 instruction set is summarized in Table 5 1 The instruction set of the CPU32 is very similar to that of the MC68020 Two new...

Page 109: ...it of destination BGND none none If background mode enabled then enter background mode else format vector offset SSP PC SSP SR SSP vector PC BKPT data none If breakpoint cycle acknowledged then execut...

Page 110: ...illegal instruction vector address PC JMP none Destination PC JSR none SP 4 SP PC SP destination PC LEA ea An 32 ea An LINK An d 16 32 SP 4 SP An SP SP An SP d SP LPSTOP1 data none Data SR interrupt...

Page 111: ...If condition true then destination bits are set to 1 else destination bits are cleared to 0 STOP1 data 16 Data SR STOP SUB ea Dn Dn ea 8 16 32 Destination Source Destination SUBA ea An 16 32 Destinat...

Page 112: ...ing is the transition from normal mode program execution to execution of a routine that deals with an exception 5 9 1 Exception Vectors An exception vector is the address of a routine that handles an...

Page 113: ...2 8 008 SD Bus Error 3 12 00C SD Address Error 4 16 010 SD Illegal Instruction 5 20 014 SD Zero Division 6 24 018 SD CHK CHK2 Instructions 7 28 01C SD TRAPcc TRAPV Instructions 8 32 020 SD Privilege V...

Page 114: ...mes contain copies of the status register and the program counter for use by RTE The type of exception and the context in which the exception occurs determine what other information is stored in the s...

Page 115: ...e CPU32 is unique in that the debugger has been implemented in CPU microcode BDM incorporates a full set of debugging options registers can be viewed or altered memory can be read or written to and te...

Page 116: ...be tagged with a breakpoint Refer to the SIM Reference Manual SIMRM AD for timing information 5 10 2 2 BDM Sources When BDM is enabled any of several sources can cause the transition from normal mode...

Page 117: ...way as external break points peripherals request breakpoints by asserting the BKPT signal Consult the appropriate peripheral user s manual for additional details on the generation of periph eral brea...

Page 118: ...n into the specified system control register Read Memory Location READ Read the sized data at the memory location specified by the long word address The source function code register SFC determines th...

Page 119: ...used the transition An example is a breakpoint on a released write The bus cycle may overlap as many as two subsequent instructions before stalling the instruction sequencer A breakpoint asserted duri...

Page 120: ...eceived simultaneously by both master and slave devices In general data transitions occur on the falling edge of DSCLK and are stable by the following rising edge of DSCLK Data is transmitted MSB firs...

Page 121: ...nitor the instruction pipeline The instruction pipe IPIPE output indicates the start of each new instruction and each mid instruction pipeline advance The instruction fetch IF ETCH output identifies t...

Page 122: ...has been added to the processor The loop mode is used by any single word instruction that does not change the program flow Loop mode is implemented in conjunction with the DBcc instruction Figure 5 1...

Page 123: ...CENTRAL PROCESSING UNIT MC68332 5 24 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 124: ...f a 256 bit data stream without CPU intervention A special wraparound mode supports continuous sampling of a serial peripheral with automatic QSPI RAM updating for efficient inter facing to A D conver...

Page 125: ...QSMCR contains parameters for interfacing to the CPU32 and the intermodule bus The QSM test register QTEST is used during fac tory test of the QSM The QSM interrupt level register QILR determines the...

Page 126: ...quest priority to determine whether it should contend for arbitration priority Arbitration priority is determined by the value of the IARB field in the QSMCR Each module that generates interrupts must...

Page 127: ...mpatible with SPI systems found on other Freescale products but has enhanced capabilities The QSPI can per NOTES 1 PQS2 is a digital I O pin unless the SPI is enabled SPE in SPCR1 set in which case it...

Page 128: ...g the command for the next serial transfer Normally the pointer address is incremented after each serial transfer but the CPU can change the pointer value at any time Multiple task support can be pro...

Page 129: ...r to APPENDIX D REG ISTER SUMMARY for register bit and field definitions QSPI BLOCK CONTROL REGISTERS END QUEUE POINTER QUEUE POINTER STATUS REGISTER DELAY COUNTER COMPARATOR PROGRAMMABLE LOGIC ARRAY...

Page 130: ...SPI can set the bits in this register The CPU reads the SPSR to obtain QSPI status information and writes it to clear status flags 6 3 2 QSPI RAM The QSPI contains an 80 byte block of dual access stat...

Page 131: ...command RAM Command RAM consists of 16 bytes Each byte is divided into two fields The periph eral chip select field enables peripherals for transfer The command control field pro vides transfer option...

Page 132: ...r nal pointer is copied into CPTQP the internal pointer is incremented and then the sequence repeats Execution continues at the internal pointer address unless the NEWQP value is changed After each co...

Page 133: ...ueue transfer to exchange data with the external device correctly Although the QSPI inherently supports multimaster operation no special arbitration mechanism is provided A mode fault flag MODF indica...

Page 134: ...GLOBAL REGISTERS CPU INITIALIZES QSPI CONTROL REGISTERS CPU INITIALIZES QSM PIN REGISTERS CPU INITIALIZES QSPI RAM CPU ENABLES QSPI BEGIN A2 INITIALIZATION OF QSPI BY THE CPU MSTR 1 A1 YES NO QSPI FLO...

Page 135: ...QP IS QSPI DISABLED NO YES EXECUTE SERIAL TRANSFER STORE RECEIVED DATA IN RAM USING QUEUE POINTER ADDRESS B1 QSPI CYCLE BEGINS MASTER MODE YES ASSERT PERIPHERAL CHIP SELECT S IS PCS TO SCK DELAY PROGR...

Page 136: ...NO WRITE QUEUE POINTER TO CPTQP STATUS BITS STORE RECEIVED DATA IN RAM USING QUEUE POINTER ADDRESS B2 QSPI CYCLE BEGINS SLAVE MODE YES EXECUTE SERIAL TRANSFER WHEN SCK RECEIVED IS SLAVE SELECT PIN AS...

Page 137: ...R TRANSFER ASSERTED EXECUTE PROGRAMMED DELAY B1 WRITE QUEUE POINTER TO CPTQP STATUS BITS C NEGATE PERIPHERAL CHIP SELECT S YES NO IS CONTINUE BIT ASSERTED EXECUTE STANDARD DELAY QSPI FLOW 4 YES NO Fre...

Page 138: ...ANGED TO NEWQP NO WRITE QUEUE POINTER TO CPTQP STATUS BITS STORE RECEIVED DATA IN RAM USING QUEUE POINTER ADDRESS C YES EXECUTE SERIAL TRANSFER WHEN SCK RECEIVED IS SLAVE SELECT PIN ASSERTED HAS NEWQP...

Page 139: ...ING QUEUE POINTER TO NEWQP OR 0000 DISABLE QSPI A1 INCREMENT WORKING QUEUE POINTER IS HALT OR FREEZE ASSERTED A2 HALT QSPI AND ASSERT HALTA IS INTERRUPT ENABLE BIT HMIE ASSERTED INTERRUPT CPU IS HALT...

Page 140: ...itiated QSM register PQSPAR must be written to assign necessary pins to the QSPI The pins necessary for master mode operation are MISO and MOSI SCK and one or more of the chip select pins MISO is used...

Page 141: ...1 2 3 127 When DSCK equals zero DSCKL is not used Instead the PCS valid to SCK transi tion is one half the DSCK period There are two transfer length options The user can choose a default value of eigh...

Page 142: ...PI requires time to load a transmit RAM entry for transfer Receiving devices need at least the standard delay between successive transfers If the system clock is operating at a slower rate the delay b...

Page 143: ...d New receive data overwrites previously received data in receive RAM Each time the end of the queue is reached the SPIF flag is set SPIF is not au tomatically reset If interrupt driven SPI service is...

Page 144: ...I drives neither the clock nor the chip select pins and thus cannot control clock rate or transfer delay Because the BITSE option is not available in slave mode the BITS field specifies the number of...

Page 145: ...must be active low PCS bit in command RAM must be cleared PORTQS bits are cleared during re set If no new data is written to PORTQS before pin assignment and configuration as an output base state of...

Page 146: ...OL LOGIC PIN BUFFER AND CONTROL H 8 7 6 5 4 3 2 1 0 L 10 11 BIT Tx SHIFT REGISTER MDDR7 MDDR5 TxD SCDR Tx BUFFER TRANSFER Tx BUFFER SHIFT ENABLE JAM ENABLE PREAMBLE JAM 1 s BREAK JAM 0 s WRITE ONLY FO...

Page 147: ...SR STATUS REGISTER PF RAF 15 0 WAKEUP LOGIC PIN BUFFER RxD STOP 8 7 6 5 4 3 2 1 0 10 11 BIT Rx SHIFT REGISTER START MSB ALL ONES DATA RECOVERY 16 PARITY DETECT RECEIVER BAUD RATE CLOCK SCDR Rx BUFFER...

Page 148: ...is a write only register that contains data to be transmitted The data is first written to the TDR then trans ferred to the transmit serial shifter where additional format bits are added before trans...

Page 149: ...es the number of bits per frame The most common ten bit data frame format for NRZ serial interface consists of one start bit eight data bits LSB first and one stop bit The most common eleven bit data...

Page 150: ...o the TDR while other data is shifted out The transmitter enable TE bit in SCCR1 en ables TE 1 and disables TE 0 the transmitter Shifter output is connected to the TXD pin while the transmitter is ope...

Page 151: ...are transmitted The TC flag is set and the TXD pin reverts to control by PQS PAR and DDRQS Buffered data is not transmitted after TE is cleared To avoid losing data in the buffer do not clear TE until...

Page 152: ...reserved but the data in the serial shifter is lost Be cause framing noise and parity errors are detected while data is in the serial shifter FE NF and PF cannot occur at the same time as OR When the...

Page 153: ...sing and recognition scheme Idle line wakeup allows a receiver to sleep until an idle line is detected When an idle line is detected the receiver clears RWU and wakes up The receiver waits for the fir...

Page 154: ...g mode MSTR e Enable or disable wired OR operation WOMQ 3 QSPI control register one SPCR1 a Establish a delay following serial transfer by writing to the DTL field b Establish a delay before serial tr...

Page 155: ...ransmitter interrupt TIE b Clear the transmitter data register empty TDRE and transmit complete TC indicators by reading the serial communication interface status reg ister SCSR c Write transmit data...

Page 156: ...TPU functions replace software functions that would require host CPU interrupt service The following pre programmed timing functions are currently available Input capture input transition counter Out...

Page 157: ...base for match and the other for capture 7 2 3 Scheduler When a service request is received the scheduler determines which TPU channel is serviced by the microengine A channel can request service for...

Page 158: ...pare functions of the channel 7 3 TPU Operation All TPU functions are related to one of the two 16 bit time bases Functions are syn thesized by combining sequences of match events and capture events B...

Page 159: ...mber To prevent a single high priority channel from permanently blocking other functions other service requests of the same priority are performed in channel order after the lowest numbered highest pr...

Page 160: ...ts The CPU recognizes only interrupt requests of a priority greater than the value con tained in the interrupt priority IP mask in the condition code register When the CPU acknowledges an interrupt re...

Page 161: ...tect a single transition or specified number of transitions then cease channel activity until reinitialization After each transition or specified number of tran sitions the channel can generate a link...

Page 162: ...is reset to FFFF Alternatively a byte at an address specified by a channel parameter can be read and used as a flag A nonzero value of the flag indicates that TCR2 is to be reset to FFFF once the next...

Page 163: ...the control state every time a new step command is received A 16 bit parameter initialized by the CPU for each channel defines the output state of the associated pin The bit pattern written by the CP...

Page 164: ...n interpolation by the host CPU between counts at very slow count rates 7 5 Motion Control Time Functions The following paragraphs describe factory programmed time functions implemented in the motion...

Page 165: ...e frequency measurement capability and the latest complete accumulation over the programmed number of periods 7 5 5 Multichannel Pulse Width Modulation MCPWM MCPWM generates pulse width modulated outp...

Page 166: ...annel during a user defined win dow period The function has single shot and continuous modes No pulses are lost between sample windows in continuous mode The user selects whether to detect pulses on t...

Page 167: ...nt register 1 prescaler control Channels using TCR1 have the capability to re solve down to the TPU system clock divided by 4 Refer to Figure 7 2 and Table 7 1 Figure 7 2 TCR1 Prescaler Control 7 6 1...

Page 168: ...TPU in emulation mode In emula tion mode the TPU executes microinstructions from TPURAM exclusively Access to the TPURAM module through the IMB by a host is blocked and the TPURAM module is dedicated...

Page 169: ...ted on the corresponding channel Encodings for predefined functions in the TPU ROM are found in Table 7 3 7 6 2 3 Host Sequence Registers The host sequence field selects the mode of operation for the...

Page 170: ...he scope of this manual Register descrip tions are provided in APPENDIX D REGISTER SUMMARY Refer to the TPU Reference Manual TPURM AD for more information Table 7 3 Channel Priority Encodings CHX 1 0...

Page 171: ...TIME PROCESSOR UNIT MC68332 7 16 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 172: ...ck begins at address 7FFB00 or FFFB00 depend ing on the value of the module mapping MM bit in the SIM configuration register SIMCR SECTION 4 SYSTEM INTEGRATION MODULE contains more information about h...

Page 173: ...A long word access re quires two bus cycles Refer to SECTION 4 SYSTEM INTEGRATION MODULE for more information concerning access times During normal operation the TPU does not access the array and has...

Page 174: ...disables the array These actions make it possible to write a new base address into the base address register When a synchronous reset occurs while a byte or word TPURAM access is in progress the acce...

Page 175: ...STANDBY RAM WITH TPU EMULATION MC68332 8 4 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 176: ...late resistance values for positive and negative clamp voltag es then use the larger of the two values 6 Power supply must maintain regulation within operating VDD range during instantaneous and opera...

Page 177: ...n Standby operation ISB 7 0 40 A A 8 Power Dissipation PD 455 mW Table A 2a Typical Ratings 20 97 MHz Operation Num Rating Symbol Value Unit 1 Supply Voltage VDD 5 0 V 2 Operating Temperature TA 25 C...

Page 178: ...ed is PD K TJ 273 C 2 Solving equations 1 and 2 for K gives K PD TA 273 C JA PD 2 3 where K is a constant pertaining to the particular part K can be determined from equation 3 by measuring PD at equil...

Page 179: ...dc 16 78 On Chip PLL System Frequency fsys 0 131 16 78 MHz External Clock Operation dc 16 78 3 PLL Lock Time2 3 4 5 tlpll 20 ms 4 VCO Frequency6 fVCO 2 fsys max MHz 5 Limp Mode Clock Frequency SYNCR...

Page 180: ...e divider is enabled and fsys fVCO 4 When X 1 the divider is disabled and fsys fVCO 2 X must equal one when operating at maximum specified fsys 7 Stability is the average deviation from the programmed...

Page 181: ...1 V 11 Data Bus Mode Select Pull up Current5 Vin VILDATA 15 0 Vin VIHDATA 15 0 IMSP 15 120 A 12 VDD Supply Current6 RUN 4 RUN TPU emulation mode LPSTOP 32 768 kHz crystal VCO Off STSIM 0 LPSTOP Extern...

Page 182: ...V 11 Data Bus Mode Select Pull up Current5 Vin VILDATA 15 0 Vin VIHDATA 15 0 IMSP 15 120 A 12 VDD Supply Current6 RUN 4 RUN TPU emulation mode LPSTOP 32 768 kHz crystal VCO Off STSIM 0 LPSTOP External...

Page 183: ...ctive pulldown device is recommended 6 Total operating current is the sum of the appropriate IDD IDDSYN and ISB values IDD values include supply cur rents for device modules powered by VDDE and VDDI p...

Page 184: ...w to IFETCH IPIPE Negated tCLIN 2 22 ns 13 AS DS CS Negated to Address FC SIZE Invalid Address Hold tSNAI 15 ns 14 AS CS Width Asserted tSWA 100 ns 14A DS CS Width Asserted Write tSWAW 45 ns 14B AS CS...

Page 185: ...s 53 Data Out Hold from Clock High tDOCH 0 ns 54 Clock High to Data Out High Impedance tCHDH 28 ns 55 R W Asserted to Data Bus Impedance Change tRADC 40 ns 56 RESET Pulse Width Reset Instruction tHRPW...

Page 186: ...Low to IFETCH IPIPE Negated tCLIN 2 22 ns 13 AS DS CS Negated to Address FC SIZE Invalid Address Hold tSNAI 10 ns 14 AS CS Width Asserted tSWA 80 ns 14A DS CS Width Asserted Write tSWAW 36 ns 14B AS C...

Page 187: ...53 Data Out Hold from Clock High tDOCH 0 ns 54 Clock High to Data Out High Impedance tCHDH 23 ns 55 R W Asserted to Data Bus Impedance Change tRADC 32 ns 56 RESET Pulse Width Reset Instruction tHRPW 5...

Page 188: ...ween multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles 7 Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on...

Page 189: ...0 VDD Figure A 2 External Clock Input Timing Diagram NOTE Timing shown with respect to 20 and 70 VDD Figure A 3 ECLK Output Timing Diagram 68300 CLKOUT TIM CLKOUT NOTE Timing shown with respect to 20...

Page 190: ...TIM CLKOUT S0 S1 S2 S3 S4 S5 54 21 11 13 8 6 A20 A23 FC0 FC2 SIZ0 SIZ1 DS CS R W AS DSACK0 DSACK1 D0 D15 BERR 20 HALT BKPT 9 15 14 12 46 17 47A 28 22 25 55 48 73 74 27A 53 26 14A 9 23 Freescale Semic...

Page 191: ...C TIM CLKOUT S0 S1 S2 S3 S4 S5 54 21 11 13 8 6 A20 A23 FC0 FC2 SIZ0 SIZ1 DS CS R W AS DSACK0 DSACK1 D0 D15 BERR 20 HALT BKPT 9 15 14 12 46 17 47A 28 22 25 55 48 73 74 27A 53 26 14A 9 23 Freescale Semi...

Page 192: ...ead Cycle Timing Diagram 68300 FAST RD CYC TIM CLKOUT S0 S1 S4 S5 S0 A0 A23 FC0 FC2 SIZ0 SIZ1 DS CS R W AS D0 D15 BKPT 8 6 14B 12 9 20 18 46A 30 27 73 29A 30A 74 29 Freescale Semiconductor I Freescale...

Page 193: ...on Write Cycle Timing Diagram 68300 FAST WR CYC TIM CLKOUT S0 S1 S4 S5 S0 A0 A23 FC0 FC2 SIZ0 SIZ1 DS CS R W AS D0 D15 BKPT 8 6 9 12 14B 20 46A 23 24 18 25 73 74 Freescale Semiconductor I Freescale Se...

Page 194: ...Timing Diagram Active Bus Case 68300 BUS ARB TIM CLKOUT S0 S1 S2 S3 S4 A0 A23 D0 D15 S98 A5 A5 A2 S5 AS DS R W DSACK0 DSACK1 BR BG BGACK 47A 35 33 37 7 16 33 39A Freescale Semiconductor I Freescale S...

Page 195: ...state insertion Figure A 10 Show Cycle Timing Diagram 68300 BUS ARB TIM IDLE CLKOUT A0 A5 A0 A23 D0 D15 A2 A3 A0 A5 BR AS BG BGACK 33 33 47A 37 47A 35 47A CLKOUT S0 S41 S42 S0 S1 S2 A0 A23 R W AS DS D...

Page 196: ...ing Diagram 68300 CHIP SEL TIM S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 CLKOUT A0 A23 FC0 FC2 SIZ0 SIZ1 AS DS CS R W D0 D15 6 6 8 11 12 13 9 9 14 11 9 14 15 25 20 18 17 12 21 17 18 21 23 29A 27 53 54 46 55...

Page 197: ...SI Input Hold Time tDSIH 10 ns B2 DSCLK Setup Time tDSCSU 15 ns B3 DSCLK Hold Time tDSCH 10 ns B4 DSO Delay Time tDSOD 25 ns B5 DSCLK Cycle Time tDSCCYC 2 tcyc B6 CLKOUT High to FREEZE Asserted Negate...

Page 198: ...Background Debugging Mode Timing Diagram Freeze Assertion 68300 BKGD DBM SER COM TIM CLKOUT FREEZE BKPT DSCLK IFETCH DSI IPIPE DSO B1 B2 B0 B9 B3 B4 B5 68300 BKGD DBM FRZ TIM CLKOUT FREEZE IFETCH DSI...

Page 199: ...11 ECLK Low to Data Valid Write tEDDW 2 tcyc E12 ECLK Low to Data Hold Write tEDHW 15 ns E13 Address Access Time Read 3 tEACC 386 ns E14 Chip Select Access Time Read 4 tEACS 296 ns E15 Address Setup T...

Page 200: ...izer control register SYNCR 0 Figure A 15 ECLK Timing Diagram 68300 E CYCLE TIM CLKOUT A0 A23 CS ECLK D0 D15 D0 D15 WRITE READ WRITE R W 2A 1A 3A E1 E2 E4 E9 E14 E13 E6 E15 E3 E10 E7 E12 E8 E11 E5 Fre...

Page 201: ...er Slave fop DC DC 1 4 1 4 System Clock Frequency System Clock Frequency 1 Cycle Time Master Slave tqcyc 4 4 510 tcyc tcyc 2 Enable Lead Time Master Slave tlead 2 2 128 tcyc tcyc 3 Enable Lag Time Mas...

Page 202: ...PD MISO INPUT MOSI OUTPUT SCK CPOL 0 OUTPUT SCK CPOL 1 OUTPUT 6 4 13 12 5 7 11 10 13 12 2 13 12 3 4 1 68300 QSPI T MAST CPHA1 DATA LSB IN MSB IN MSB OUT MSB IN MSB OUT DATA LSB OUT PORT DATA PCS0 PCS3...

Page 203: ...UT MISO OUTPUT MOSI INPUT SCK CPOL 0 INPUT SCK CPOL 1 INPUT 11 13 12 5 6 12 2 13 12 3 4 1 9 8 10 4 11 7 13 PD 68300 QSPI T SLV CPHA1 DATA SLAVE MSB MSB IN DATA LSB IN SS INPUT MISO OUTPUT MOSI INPUT S...

Page 204: ...Min Max Unit 1 CLKOUT High to TPU Output Channel Valid tCHTOV 2 23 ns 2 CLKOUT High to TPU Output Channel Hold tCHTOH 0 20 ns 3 TPU Input Channel Pulse Width tTIPW 4 tcyc Table A 11 20 97 MHz Time Pro...

Page 205: ...ELECTRICAL CHARACTERISTICS MC68332 A 30 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 206: ...formation to be used as a guide when ordering The MC68332 is available in either a 132 pin or 144 pin plastic surface mount pack age This appendix provides package pin assignment drawings dimensional...

Page 207: ...DS CSBOOT BGACK C BG CS1 BR CS0 VSTBY 51 17 117 16 15 14 13 12 11 10 9 8 7 6 5 4 3 131 130 129 128 127 126 125 124 123 122 121 120 119 118 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 7...

Page 208: ...1 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 31 32 33 34 35 36 BGACK CS2 BG CS1 BR CS0 CSBOOT DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 NC DATA8 NC DATA9 DATA10 NC DATA11 V SS DATA12...

Page 209: ...C68332 B 4 USER S MANUAL Case outlines number 831A 01 issue A 863C 01 issue O and 918 02 issue A are available on the web at Freescale Semiconductor I Freescale Semiconductor Inc For More Information...

Page 210: ...332GVFC20 40 to 125 C 16 MHz 2 pc tray SPAKMC332GMFC16 36 pc tray MC68332GMFC16 20 MHz 2 pc tray SPAKMC332GMFC20 36 pc tray MC68332GMFC20 Std w enhanced PPWA 40 to 85 C 16 MHz 2 pc tray SPAKMC332ACFC1...

Page 211: ...MC68332GMFV20 Std w enhanced PPWA 40 to 85 C 16 MHz 2 pc tray SPAKMC332ACFV16 44 pc tray MC68332ACFV16 20 MHz 2 pc tray SPAKMC332ACFV20 44 pc tray MC68332ACFV20 40 to 105 C 16 MHz 2 pc tray SPAKMC332A...

Page 212: ...ay SPAKMC332GMPV20 60 pc tray MC68332GMPV20 Std w enhanced PPWA 40 to 85 C 16 MHz 2 pc tray SPAKMC332ACPV16 60 pc tray MC68332ACPV16 20 MHz 2 pc tray SPAKMC332ACPV20 60 pc tray MC68332ACPV20 40 to 105...

Page 213: ...MECHANICAL DATA AND ORDERING INFORMATION MC68332 B 8 USER S MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 214: ...probes available let your MMDS emulate a variety of different MCUs Contact your Freescale sales rep resentative who will assist you in selecting and configuring the modular system that fits your needs...

Page 215: ...M EEPROM 32K x 16 64K x 16 128K x 16 256K x 16 or 512K x 16 Fast RAM 32K x 16 or 128K x 16 Background mode operation for detailed operation from a personal computer platform without an on board monito...

Page 216: ...egisters block is located in the system mem ory map When MM 0 register addresses range from 7FF000 to 7FFFFF when MM 1 register addresses range from FFF000 to FFFFFF In the module memory maps in this...

Page 217: ...D7 3116 150 A0 A1 A2 A3 ADDRESS REGISTERS A4 A5 A6 3116 150 A7 USP USER STACK POINTER 310 PC PROGRAM COUNTER 70 CCR CONDITION CODE REGISTER 3116 150 A7 SSP SUPERVISOR STACK POINTER 158 70 CCR SR STATU...

Page 218: ...xtend Flag Used in multiple precision arithmetic operations In many instructions it is set to the same value as the C bit N Negative Flag Set when the MSB of a result register is set Z Zero Flag Set w...

Page 219: ...8 NOT USED NOT USED S YFFA2A NOT USED NOT USED S YFFA2C NOT USED NOT USED S YFFA2E NOT USED NOT USED S YFFA30 TEST MODULE MASTER SHIFT A TSTMSRA S YFFA32 TEST MODULE MASTER SHIFT B TSTMSRB S YFFA34 TE...

Page 220: ...Enabled 0 IMB is not available to an external master 1 An external bus master has direct access to the IMB SHEN 1 0 Show Cycle Enable This field determines what the EBI does with the external bus dur...

Page 221: ...es system clock operating frequency and mode of operation Clock frequency is determined by SYNCR bit settings as follows W Frequency Control VCO 0 Base VCO frequency 1 VCO frequency multiplied by four...

Page 222: ...ert reset signals at the same time more than one bit in RSR may be set This register can be read at any time a write has no effect EXT External Reset Reset caused by an external signal POW Power Up Re...

Page 223: ...rresponding pin as an input This register can be read or written at any time D 2 8 PEPAR Port E Pin Assignment Register YFFA17 Bits in this register determine the function of port E pins Setting a bit...

Page 224: ...orresponding pin as an input This register can be read or written at any time D 2 11 PFPAR Port F Pin Assignment Register YFFA1F Bits in this register determine the function of port F pins Setting a b...

Page 225: ...nitor Enable 0 Disable halt monitor function 1 Enable halt monitor function BME Bus Monitor External Enable 0 Disable bus monitor function for an internal to external bus cycle 1 Enable bus monitor fu...

Page 226: ...c timer clock prescaled by a value of 512 PITM 7 0 Periodic Interrupt Timing Modulus This is the 8 bit timing modulus used to determine periodic interrupt rate Use the fol lowing expression to calcula...

Page 227: ...ctions of corresponding chip select pins CSPAR0 15 14 are not used These bits always read zero write has no effect CSPAR0 bit 1 always reads one writes to CSPAR0 bit 1 have no effect The alternate fun...

Page 228: ...izes differ ADDR 23 11 Base Address This field sets the starting address of a particular address space 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 CSPA1 4 CSPA1 3 CSPA1 2 CSPA1 1 CSPA1 0 RESET 0...

Page 229: ...d R W Read Write This field causes a chip select to be asserted only for a read only for a write or for both read and write STRB Address Strobe Data Strobe 0 Address strobe 1 Data strobe DSACK Data St...

Page 230: ...ister Function Summary MODE BYTE R W STRB DSACK SPACE IPL AVEC 0 ASYNC 00 Disable 00 Rsvd 0 AS 0000 0 WAIT 00 CPU SP 000 All 0 Off 1 SYNC 01 Lower 01 Read 1 DS 0001 1 WAIT 01 User SP 001 Priority 1 1...

Page 231: ...Field 0 TPURAM array is accessible from the supervisor or user privilege level 1 TPURAM array is accessible from the supervisor privilege level only D 3 2 TRAMTST TPURAM Test Register YFFB02 TRAMTST i...

Page 232: ...ed The TPURAM array is disabled by internal logic after a master reset Writing a valid base address to the RAM array base address field bits 15 3 automatically clears RAMDS enabling the RAM array Free...

Page 233: ...s to QSPI RAM or any register are guaranteed valid STOP is set during Table D 4 QSM Address Map Access Address 15 8 7 0 S YFFC00 QSM MODULE CONFIGURATION QSMCR S YFFC02 QSM TEST QTEST S YFFC04 QSM INT...

Page 234: ...n it responds to an interrupt acknowledge cycle At reset QIVR is initialized to vector number 0F the uninitialized interrupt vector number To use in terrupt driven serial communication a user defined...

Page 235: ...C0A SCCR1 contains SCI configuration parameters including transmitter and receiver en able bits interrupt enable bits and operating mode enable bits The CPU can read and write SCCR1 at any time The SC...

Page 236: ...e 0 SCI RDRF and OR interrupts inhibited 1 SCI RDRF and OR interrupts enabled ILIE Idle Line Interrupt Enable 0 SCI IDLE interrupts inhibited 1 SCI IDLE interrupts enabled TE Transmitter Enable 0 SCI...

Page 237: ...ad or write of register SCDR TDRE Transmit Data Register Empty 0 Register TDR still contains data to be sent to the transmit serial shifter 1 A new character can now be written to register TDR TC Tran...

Page 238: ...t operation R8 T8 have no meaning or effect D 4 8 PORTQS Port QS Data Register YFFC15 PORTQS latches I O data Writes drive pins defined as outputs Reads return data present on the pins To avoid drivin...

Page 239: ...Field PQSPAR Bit Pin Function PQSPA0 0 PQS0 1 MISO PQSPA1 0 PQS1 1 MOSI PQSPA2 0 PQS21 1 SCK PQSPA3 0 PQS3 1 PCS0 SS PQSPA4 0 PQS4 1 PCS1 PQSPA5 0 PQS5 1 PCS2 PQSPA6 0 PQS6 1 PCS3 PQSPA7 0 PQS72 1 TXD...

Page 240: ...case it becomes SCI serial output TXD Effect of DDRQS on QSM Pin Function QSM Pin Mode DDRQS Bit Bit State Pin Function MISO Master DDQS0 0 Serial Data Input to QSPI 1 Disables Data Input Slave 0 Disa...

Page 241: ...egister 1 YFFC1A SPCR1 enables the QSPI and specified transfer delays The CPU32 has read write access to SPCR1 but the QSM has read access only to all bits but enable bit SPE SPCR1 must be written las...

Page 242: ...s field contains the first QSPI queue address D 4 13 SPCR3 QSPI Control Register 3 YFFC1E SPSR QSPI Status Register YFFC1F SPCR3 contains the loop mode enable bit halt and mode fault interrupt enables...

Page 243: ...Data RAM YFFD00 YFFD0E Data received by the QSPI is stored in this segment The CPU32 reads this segment to retrieve data from the QSPI Data stored in receive RAM is right justified Unused bits in a re...

Page 244: ...pheral chip can be connected to each PCS pin provided proper fanout is ob served PCS0 shares a pin with the slave select SS signal which initiates slave mode serial transfer If SS is taken low when th...

Page 245: ...7 0 S YFFE00 TPU MODULE CONFIGURATION REGISTER TPUMCR S YFFE02 TEST CONFIGURATION REGISTER TCR S YFFE04 DEVELOPMENT SUPPORT CONTROL REGISTER DSCR S YFFE06 DEVELOPMENT SUPPORT STATUS REGISTER DSSR S Y...

Page 246: ...the external TCR2 pin functions as a gate of the DIV8 clock the TPU system clock divided by eight In this case when the external TCR2 pin is low the DIV8 clock is blocked preventing it from incrementi...

Page 247: ...r during the time slot transition period CLKS Stop Clocks to TCRs 0 Do not stop TCRs 1 Stop TCRs during the halted state FRZ 1 0 IMB FREEZE Response The FRZ bits specify the TPU microengine response t...

Page 248: ...because of a PC register match with the PC breakpoint register PCBK is negated when the BKPT flag is negated CHBK Channel Register Breakpoint Flag CHBK is asserted if a breakpoint occurs because of a...

Page 249: ...ion Select Register 1 YFFE0E D 5 9 CFSR2 Channel Function Select Register 2 YFFE10 D 5 10 CFSR3 Channel Function Select Register 3 YFFE12 CHANNEL 15 0 Encoded Time Function for each Channel Encoded fo...

Page 250: ...ce is completed by the microengine on that channel The host can request service on a channel by writ ing the corresponding host service request field to one of three nonzero states The CPU should moni...

Page 251: ...0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHX 1 0 Service Guaranteed Time Slots 00 Disabled 01 Low 1 out of...

Page 252: ...H 14 CH 13 CH 12 CH 11 CH 10 CH 9 CH 8 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table D 6 Parameter RAM Address Map Channel Base Parameter Number Address 0 1 2 3 4...

Page 253: ...ITR S FFFA26 NOT USED SOFTWARE SERVICE SWSR S FFFA28 NOT USED NOT USED S FFFA2A NOT USED NOT USED S FFFA2C NOT USED NOT USED S FFFA2E NOT USED NOT USED S FFFA30 TEST MODULE MASTER SHIFT A TSTMSRA S FF...

Page 254: ...ONFIGURATION REGISTER TRAMMCR S FFFB02 TPURAM TEST REGISTER TRAMTST S FFFB04 TPURAM BASE ADDRESS AND STATUS REGISTER TRAMBAR S FFFB06 NOT USED QSM Access Address 15 8 7 0 S FFFC00 QSM MODULE CONFIGURA...

Page 255: ...QUEST REGISTER 0 HSRR0 S U FFFE1A HOST SERVICE REQUEST REGISTER 1 HSRR1 S FFFE1C CHANNEL PRIORITY REGISTER 0 CPR0 S FFFE1E CHANNEL PRIORITY REGISTER 1 CPR1 S FFFE20 CHANNEL INTERRUPT STATUS REGISTER C...

Page 256: ...CH 15 0 Channel Priority CPR 0 1 CH 15 0 Service Status DCNR CH 15 0 Encoded Host Sequence HSQR 0 1 CH 15 0 Host Service Request HSRR 0 1 CH 15 0 Link LR CH 15 0 Service Granted SGLR CHBK Channel Regi...

Page 257: ...SCCR1 MM Module Mapping SIMCR MODE Asynchronous Synchronous Mode CSOR 0 10 CSORBT MODF Mode Fault Flag SPSR MSTR Master Slave Mode Select SPCR0 N Negative Flag CCR NEWQP New Queue Pointer Value SPCR2...

Page 258: ...st Breakpoint Flag DSSR STEXT Stop Mode External Clock SYNCR STF Stop Flag TPUMCR STOP Stop Enable QSMCR TPUMCR TRAMMCR STRB Address Strobe Data Strobe CSOR 0 10 CSORBT STSIM Stop Mode System Integrat...

Page 259: ...OR Mode for SCI Pins SCCR1 WREN Wrap Enable SPCR2 WRTO Wrap To SPCR2 X Extend CCR X Frequency Control Bit Prescale SYNCR Y 5 0 Frequency Control Counter SYNCR Z Zero Flag CCR Table D 8 Register Bit an...

Page 260: ...in package and 144 pin package pin assign ment diagrams drawn Pages 3 6 3 7 Revised pin characteristics Page 3 8 Incorporated VDD VSS breakout information Pages 3 9 3 11 Revised signal characteristics...

Page 261: ...and bit mnemonics consistent Appendix a Electrical Characteristics Pages A 1 A 30 Completely revised electrical characteristics section Add ed 20 97 MHz timing parameters Appendix B Mechanical Data a...

Page 262: ...p selects peripheral 6 22 Chip select block 4 1 Chip select operation 4 55 Chip select pins 4 51 CIER 7 14 CIRL 7 5 CISR 7 11 7 14 Clock mode MODCLK 4 10 Clock synthesizer control register SYNCR 4 10...

Page 263: ...e 5 23 Instruction set 5 9 Instructions ABCD 5 4 BCD 5 4 low power stop 5 13 MOVEC 5 6 NBCD 5 4 SBCD 5 4 special 5 9 TBL 5 13 instructions MOVES 5 6 Intermodule bus IMB 3 9 Internal bus monitor 4 5 In...

Page 264: ...r 6 25 Port QS pin assignment register PQSPAR 6 3 PORTC 4 55 PORTE 4 58 PORTF 4 58 PORTQS 6 4 PQSPAR 6 3 6 17 6 20 6 25 Privilege level supervisor 5 5 Privilege levels 5 9 user supervisor 5 2 Processi...

Page 265: ...ipheral interface protocol 5 21 SHEN 4 37 Short idle line detection 6 29 SIM 1 1 3 1 4 1 SIM configuration register SIMCR 4 3 SIMCLK 4 16 SIMCR 3 10 4 3 SIZ0 4 19 SIZ1 4 19 Slave enable SLVEN 4 4 Slav...

Page 266: ...it data TXD 6 25 Transmit interrupt enable TIE 6 28 Transmit RAM 6 8 Transmitter enable TE 6 27 TXD 6 25 6 27 U Uninitialized interrupt vector 6 3 User data space 4 4 User privilege level 5 2 User sta...

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