Hardware Reference
Low-Voltage Inhibit (LVI)
M68HC12A4EVB Evaluation Board — Rev. 1
User’s Manual
MOTOROLA
Hardware Reference
91
4.11 Low-Voltage Inhibit (LVI)
Low-voltage inhibit (LVI) uses a Motorola undervoltage sensing device (U1) to
automatically drive the MCU’s RESET pin low whenever V
DD
is below legal
limits (2.8 Vdc typical). This prevents the accidental corruption of EEPROM
data if the power-supply voltage should drop below the allowable level. Header
W1 allows for the disconnection of the LVI circuit.
4.12 Analog-to-Digital (A/D) Converter
The MCU’s A/D converter is fully documented in the MC68HC812A4
Technical Summary, Motorola document order number MC68HC812A4TS/D.
NOTE:
Two of the A/D bus lines, PAD0 and PAD1, are used by the EVB and D-Bug12
for configuration purposes. These lines are not available for A/D usage in the
factory-default configuration.
The accuracy of the A/D converter can be increased by supplying the MCU’s
A/D circuitry with the same supply voltages used by the target hardware. These
supply lines (V
DDA
and V
SSA
) and the associated A/D reference voltages (V
RH
and V
RL
) can be isolated from the EVB’s power bus with cut-trace footprints
W15, W16, W17, and W18. Refer to the EVB schematic diagram for details.
4.13 Background Debug Mode (BDM) Interface
The MCU’s serial BDM interface can be accessed through J5, a 2-row x 3-pin
header. The pin assignments are shown in
Table 4-4
.
NOTE:
The BDM interface requires a development tool such as Motorola’s serial
debug interface. For more information, refer to
Appendix F. SDI
Configuration
and to the Serial Debug Interface User’s Manual, Motorola
document order number SDIUM/D.
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