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User’s Manual

M68HC12A4EVB Evaluation Board — Rev. 1

Hardware Reference

MOTOROLA

Hardware Reference

W32

(2)

ROM Pin Assignment — Pin 28 of 32-pin package

or pin 26 of 28-pin package

1–2
3–4
5–6

Pin is connected to MCU address line A13 for narrow modes.
Pin is connected to MCU address line A14 for wide modes.
Pin is connected to V

to enable the device’s chip enable (CE2).

W33

(2)

ROM Pin Assignment — Pin 3 of 32-pin package

or pin 1 of 28-pin package

1–2
3–4
5–6

Pin is connected to MCU address line A15 for narrow modes.
Pin is connected to MCU address line A16 for wide modes.
Pin is connected to V

for ROM program voltage (V

W34

(3)

MCU MODB Select

1–2
2–3

MCU’s PE6/MODB pin is connected to V

W36

(2)

ROM Pin Assignment — Pin 2 of 32-pin package

1–2
3–4
5–6

Pin is connected to MCU address line A16 — for narrow modes.
Pin is connected to MCU address line A17 — for wide modes.
Pin is connected to V

W42

(3)

MCU MODA Select

1–2
2–3

MCU’s PE5/MODA pin is connected to V

Table 4-1. Jumper-Selectable Functions (Sheet 4 of 4)

Diagram

Setting

Description

(1)

W12 and W13 together select the type of RAM installed.

(2)

W22, W24, W29, W32, W33, and W36 together select the type of ROM installed.

(3)

W30, W34, and W42 together determine the MCU’s mode of operation.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

IVE

D B

Y F

Summary of Contents for M68HC12A4EVB

Page 1: ...ALUATION BOARD USER S MANUAL M68HC12A4EVBUM D October 1999 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 2: ...ness for a particular purpose Motorola makes no representation that the interconnection of products in the manner described herein will not infringe on existing or future patent rights nor do the descriptions contained herein imply the granting or license to make use or sell equipment constructed in accordance with this description Trademarks This document includes these trademarks Motorola and th...

Page 3: ...tion 4 Hardware Reference 77 Appendix A S Record Format 117 Appendix B Communications Program Examples 123 Appendix C D Bug12 Startup Code 131 Appendix D D Bug12 Customization Data 135 Appendix E Customizing the EPROMs 141 Appendix F SDI Configuration 143 Glossary 145 Index 149 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARC...

Page 4: ... Evaluation Board Rev 1 4 List of Sections MOTOROLA List of Sections Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 5: ...ns 23 1 8 Typographic Conventions 24 1 9 Customer Support 25 Section 2 Configuration and Setup 2 1 Contents 27 2 2 Unpacking and Preparation 27 2 3 EVB Configuration 28 2 4 EVB to Power Supply Connection 29 2 5 EVB to Terminal Connection 29 2 6 Terminal Communications Setup 31 2 6 1 Communication Parameters 31 2 6 2 Dumb Terminal Setup 31 2 6 3 Host Computer Setup 31 2 6 4 Changing the Baud Rate 3...

Page 6: ...PROM 51 CALL Call Subroutine 52 G Go Execute a User Program 53 GT Go Till 54 HELP Onscreen Help Summary 55 LOAD Load S Record File 56 MD Memory Display 57 MDW Display Memory as 16 Bit Word 58 MM Memory Modify 59 MMW Modify 16 Bit Memory Word 60 MOVE Move Memory Block 61 NOBR Remove Breakpoints 62 RD Register Display 63 RM Register Modify 64 T Trace 65 UPLOAD Display Memory in S Record Format 67 VE...

Page 7: ... 4 3 Configuration Headers and Jumper Settings 78 4 4 Power Input Circuitry 83 4 5 Terminal Interface 83 4 6 Microcontroller 84 4 7 Memory 86 4 7 1 Memory Types and Sockets 86 4 7 2 Chip Selects 88 4 7 3 Glue Logic 89 4 8 Clock Circuitry 90 4 9 Phase Locked Loop PLL 90 4 10 Reset 90 4 11 Low Voltage Inhibit LVI 91 4 12 Analog to Digital A D Converter 91 4 13 Background Debug Mode BDM Interface 91 ...

Page 8: ...2 Introduction 124 B 3 Procomm for DOS IBM PC 124 B 3 1 Setup 124 B 3 2 S Record Transfers to EVB Memory 126 B 4 Kermit for DOS IBM PC 126 B 4 1 Setup 126 B 4 2 S Record Transfers to EVB Memory 127 B 5 Kermit Sun Workstation 127 B 5 1 Setup 127 B 5 2 S Record Transfers to EVB Memory 128 B 6 MacTerminal Apple Macintosh 128 B 6 1 Setup 128 B 6 2 S Record Transfers to EVB Memory 129 B 7 Red Ryder App...

Page 9: ...ser CPU Register Values 136 D 2 4 SysClk Field 137 D 2 5 IOBase Field 137 D 2 6 SCIBaudRegVal Field 137 D 2 7 EEBase and EESize Fields 138 D 2 8 EEPROM Erase Program Delay Function Pointer Field 138 D 2 9 Auxiliary Command Table Entries 138 Appendix E Customizing the EPROMs Appendix F SDI Configuration Glossary Index Freescale Semiconductor I Freescale Semiconductor Inc For More Information On Thi...

Page 10: ...Evaluation Board Rev 1 10 Table of Contents MOTOROLA Table of Contents Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 11: ...agram 19 2 1 EVB Power Connector J6 29 4 1 Memory Sockets Configuration 87 4 2 Chip Select Header 88 4 3 RAM ROM Logic Diagram 89 4 4 Prototype Area Component Side View 93 4 5 MCU Connector J8 Component Side View 94 4 6 MCU Connector J9 Component Side View 95 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE ...

Page 12: ...B Evaluation Board Rev 1 12 List of Figures MOTOROLA List of Figures Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 13: ...figuration Memory Map 74 4 1 Jumper Selectable Functions 79 4 2 CPU Mode Selection 85 4 3 EVB Memories Supplied 88 4 4 BDM Connector J5 Pin Assignments 92 4 5 MCU Connector J8 Pin Assignments 96 4 6 MCU Connector J9 Pin Assignments 98 A 1 S Record Fields 118 A 2 S Record Field Contents 118 A 3 S Record Types 119 A 4 S0 Header Record 120 A 5 S1 Header Record 121 A 6 S9 Header Record 122 E 1 Physica...

Page 14: ...VB Evaluation Board Rev 1 14 List of Tables MOTOROLA List of Tables Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 15: ...e M68HC12A4EVB evaluation board EVB an evaluation debugging and code generation tool for the MC68HC812A4 microcontroller units MCU Reference items such as schematic diagrams and parts lists are shipped as part of the EVB package 1 3 General Description and Features The EVB is an economical tool for designing and debugging code for and evaluating the operation of the M68HC12 MCU Family By providing...

Page 16: ...and U9A containing the D Bug12 monitor program Two memory sockets populated with two 8 Kbyte x 8 bit SRAMs U4 and U6A Support for up to 1 MByte of program space and 512 Kbytes of data space using optional memory configurations 16 MHz crystal controlled clock oscillator Y2 in a socket that can accommodate optional 8 or 14 pin oscillator chips XY2 Headers for jumper selection of hardware options for...

Page 17: ...13 and E14 2 row x 3 pin header J5 provides a connector for using background debug development tools such as the serial debug interface SDI Phase locked loop PLL biasing circuitry for altering the MCU s timebase Firmware features include D Bug12 monitor debugger program resident in external EPROM erasable programmable read only memory Full support for either dumb terminal or host computer terminal...

Page 18: ... Information MOTOROLA General Information Figure 1 1 EVB Layout and Component Placement PROTOTYPE AREA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 19: ...the MCU s RAM chip select to insert one wait state into each access of external RAM Thus when programs are run from PROTO TYPE AREA J8 J9 S1 RESET MCU MC68HC812A4 M68HC12A4EVB SCI0 SCI1 ON CHIP EEPROM RAM ON CHIP 112 PINS TOTAL RS 232C TRANSCEIVER J3 J2 J6 J5 TERMINAL SPARE POWER BDM INTERFACE S2 PROGRAM ABORT CLOCK EXTERNAL ROM AND RAM GLUE LOGIC EXTAL XTAL XFC VDD 6 VSS 6 PA 7 0 PB 7 0 PC 7 0 PD...

Page 20: ...he addresses of the EVB s different memory areas 1 5 Functional Overview The EVB is factory configured to execute D Bug12 the EPROM resident monitor program without further configuration by the user It is ready for use with an RS 232C terminal for writing and debugging user code Follow the setup instructions in Section 2 Configuration and Setup to prepare for operation Optionally the EVB can accom...

Page 21: ...code For small programs or subroutines D Bug12 s single line assembler disassembler may be used to place object code directly into the EVB s memory For larger programs the Motorola MCUez assembler may be used on a host computer to generate S record object files which then can be loaded into the EVB s memory using D Bug12 s LOAD command The EVB features a prototype area which allows custom interfac...

Page 22: ...that use external memory If an application program uses on chip RAM and EEPROM exclusively for instance if external memory is not used the clock speed can remain at 16 MHz with a supply voltage of 3 0 Vdc User terminal Options RS 232C dumb terminal Allows single line on board code assembly and disassembly Host computer with RS 232C serial port Allows off board code assembly that can be loaded into...

Page 23: ...ytes 32 64 128 256 or 512 Kbytes 64 128 256 or 512 Kbytes 32 64 128 or 256 Kbytes MCU I O ports HCMOS compatible Background debug mode interface 2 row x 3 pin header Communications ports Two RS 232C DCE ports Power requirements 16 MHz clock source 8 MHz clock source 3 5 to 5 0 Vdc 150 mA max fuse protected 1 5 A 3 0 to 5 0 Vdc 150 mA max fuse protected 1 5 A Prototype area Area Holes 2 inches x 8 ...

Page 24: ... entered by the user n argument In code the user s entry is underlined This underlining does not actually appear onscreen A typical example looks like this baud 9600 User s entry Change Terminal BR D Bug12 s response Press Return D Bug12 prompt for next entry Window names and parts of windows are indicated in initial caps unless the name of the window is capitalized in a unique way Memory and Code...

Page 25: ...uliarity INPUTx UNDO LOADMAP Menu names options and tabs and dialog edit text and lists boxes are indicated in Times bold Do this by checking the Main File option in the Environment Settings dialog s General Options tab Open the Open File dialog Select the filename in the File Name list and use the filename in the Main filename edit box 1 9 Customer Support To obtain information about technical su...

Page 26: ...aluation Board Rev 1 26 General Information MOTOROLA General Information Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 27: ...p 31 2 6 4 Changing the Baud Rate 32 2 7 Using Fast External RAM 32 2 7 1 Selecting and Replacing the RAM Chips 32 2 7 2 Reprogramming the RAM Chip Select 33 2 2 Unpacking and Preparation Before beginning configuration and setup of the EVB 1 Verify that these items are present in the EVB package M68HC12A4EVB board assembly Warranty and registration cards EVB schematic diagram and parts list M68HC1...

Page 28: ...tory configured to operate with D Bug12 it is not necessary to change any of the jumper settings to begin operating immediately Only one jumper header W20 should be changed during the course of factory default EVB operation with D Bug12 Pins 2 and 3 jumpered default Normal execution mode D Bug12 is executed from external EPROM upon reset The D Bug12 prompt appears immediately on the terminal displ...

Page 29: ...ch wire s insulation 1 4 inch from the end lift the J6 contact lever to release tension on the contact insert the bare end of the wire into J6 and close the lever to secure the wire Observe the polarity carefully CAUTION Do not use wire larger than 20 AWG in connector J6 Larger wire could damage the connector Figure 2 1 EVB Power Connector J6 2 5 EVB to Terminal Connection For factory default oper...

Page 30: ...nes must be cross connected as shown in Table 2 1 Commercial null modem adapter cables are available for this purpose Optionally the MCU s background debug mode BDM interface can serve as the user interface This setup makes both of the SCI ports available for user applications Additional hardware and software are required For more information refer to the documentation for the background debug dev...

Page 31: ...bility to generate code off board for subsequent loading into the EVB s memory It is thus desirable for the host to be capable of running programs such as Motorola s MCUez assembler For more information see 3 8 Off Board Code Generation To serve as the EVB s terminal the host computer must have an RS 232C serial port and an installed communications program capable of operating with the parameters ...

Page 32: ...clock speed 8 MHz E clock with no wait states two operations are required 1 Replace the SRAM chips with suitably fast parts See 2 7 1 Selecting and Replacing the RAM Chips 2 Reprogram the SRAM chip select CSD for zero wait state operation See 2 7 2 Reprogramming the RAM Chip Select 2 7 1 Selecting and Replacing the RAM Chips The replacement 8 Kbyte x 8 bit SRAM devices should have a chip select ac...

Page 33: ...tory supplied one time programmable OTP EPROM U7 An EPROM programmer is required NOTE Method B does not work in reverse If U7 has already been reprogrammed using this technique it cannot be restored to its original state If the EPROMs are to be customized in some other way for example to add a user program or to modify another aspect of D Bug12 the change to register CSSTR0 can be made in the star...

Page 34: ... copy of its contents to a disk file for backup purposes 4 Change the contents of the programmer s editable RAM buffer at location 7ED6 from 05 to 04 5 Reprogram U7 with the edited contents of the programmer s RAM buffer 6 Reinstall U7 in its socket on the EVB Be sure that its pins align with the rightmost end of its socket as viewed in Figure 1 1 EVB Layout and Component Placement 7 Apply power t...

Page 35: ...ep 1 5 Reinstall U7 in its socket on the EVB Be sure that its pins align with the rightmost end of its socket as viewed in Figure 1 1 EVB Layout and Component Placement 6 Apply power to the EVB and press S1 the reset switch The D Bug12 prompt should appear on the terminal display 7 Ensure that the modification was performed properly by using D Bug12 s MD MEMORY DISPLAY command to examine the CSSTR...

Page 36: ...tion Board Rev 1 36 Configuration and Setup MOTOROLA Configuration and Setup Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 37: ...o Execute a User Program 53 GT Go Till 54 HELP Onscreen Help Summary 55 LOAD Load S Record File 56 MD Memory Display 57 MDW Display Memory as 16 Bit Word 58 MM Memory Modify 59 MMW Modify Memory in 16 Bit Word 60 MOVE Move Memory Block 61 NOBR Remove Breakpoints 62 RD Register Display 63 RM Register Modify 64 T Trace 65 UPLOAD Display Memory in S Record Format 67 VERF Verify S Record File Against ...

Page 38: ...factory default or with user code in on chip EEPROM Set the jumper on header W20 accordingly See 2 3 EVB Configuration and 3 7 Alternate Execution from EEPROM 3 Connect the EVB to the external power supply See 2 4 EVB to Power Supply Connection 4 Connect the EVB to the terminal See 2 5 EVB to Terminal Connection 5 Configure the terminal communications interface See 2 6 Terminal Communications Setu...

Page 39: ...or more information refer to 3 7 Alternate Execution from EEPROM Control can be returned to the D Bug12 terminal prompt by doing one of these 1 Terminating the user code with appropriate instructions see 3 7 Alternate Execution from EEPROM 2 Activating the program abort function see 3 4 Program Abort 3 3 Reset EVB operation can be restarted at any time by activating the hardware reset function Do ...

Page 40: ...n the prototype area activate it in accordance with the custom circuitry NOTE If the EVB is configured to begin execution from on chip EEPROM D Bug12 jumps to the starting EEPROM address before performing all of its initialization and is thus not operable Do not activate the program abort function under these conditions Instead move the jumper on header W20 to pins 2 and 3 and activate the reset f...

Page 41: ...ic fields unless noted otherwise are interpreted as hexadecimal Command line entries are case insensitive and may be typed using any combination of upper and lower case letters A maximum of 80 characters including the terminating carriage return may be entered on the command line After the 80th character D Bug12 automatically terminates the command line entry and processes the characters entered t...

Page 42: ...dAddress Display Memory as 16 Bit Word Display memory contents in hex words ASCII format MM Address data Memory Modify Interactively examine change memory contents MMW address data Modify 16 Bit Memory Word Interactively examine change memory contents MOVE StartAddress EndAddress DestAddress Move a block of memory NOBR Address Address Remove individual user breakpoints RD Register Display Display ...

Page 43: ...erminal display NOTE For clarity the user s entry is underlined This underlining does not actually appear onscreen A typical example looks like this baud 9600 User s entry Change Terminal BR Press Return D Bug12 response D Bug12 prompt for next entry Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICOND...

Page 44: ...field are interpreted as signed decimal numbers Placing a in front of any number will cause the number to be interpreted as a hexadecimal number When an instruction is disassembled and displayed the D Bug12 prompt is displayed following the disassembled instruction If a carriage return is the first non space character entered following the prompt the next instruction in memory is disassembled and ...

Page 45: ...ns the number placed in the operand field should be the absolute destination address of the instruction The assembler calculates the two s complement offset of the branch and places the offset in memory with the instruction The assembly disassembly process may be terminated by entering a period as the first non space character following the assembler prompt Restrictions None Table 3 2 M68HC11 to C...

Page 46: ...nce of a leading minus sign indicates a positive number A leading plus sign is not allowed Hexadecimal numbers must be entered with a leading dollar sign followed by one to four hexadecimal digits The default number base is decimal For all branching instructions Bcc LBcc BRSET BRCLR DBEQ DBNE IBEQ IBNE TBEQ and TBNE the number entered as the branch address portion of the operand field is the absol...

Page 47: ... offsets used with indexed addressing modes are disassembled as signed decimal numbers All addresses whether direct or extended are disassembled as 4 digit hexadecimal numbers All 8 bit mask values BRSET BRCLR ANDCC ORCC are disassembled as 2 digit hexadecimal numbers All 8 bit immediate values are disassembled as hexadecimal numbers All 16 bit immediate values are disassembled as hexadecimal numb...

Page 48: ...I baud rate divider value for the requested baud rate is calculated using the M clock value supplied in the customization data area Because the SCI baud rate divider is a 13 bit counter certain baud rates may not be supported at particular M clock frequencies If the value calculated for the SCI s baud rate divider is equal to 0 or greater than 8191 command execution is terminated and the communica...

Page 49: ...LL command is used to place a single 8 bit value into a range of memory locations StartAddress is the first memory location written with data and EndAddress is the last memory location written with data If the data parameter is omitted the memory range is filled with the value 00 Restrictions None Example BF 6400 6fff 0 BF 6f00 6fff 55 Freescale Semiconductor I Freescale Semiconductor Inc For More...

Page 50: ...point addresses will display all the currently set breakpoints Restrictions D Bug12 implements the breakpoint function by replacing the instruction opcode at the breakpoint address in the user s program with an SWI instruction For this reason a breakpoint may not be set on a user SWI instruction Breakpoints may only be set at an opcode address and breakpoints may only be placed at memory addresses...

Page 51: ... erase the entire contents of the on chip EEPROM in a single operation After the bulk erase operation has been performed each on chip EEPROM location is checked for an erased condition Restrictions None Example BULK Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 52: ...current value of the PC is used as the starting address NOTE No user breakpoints are placed in memory before execution is transferred to user code Restrictions If the called subroutine modifies the value of the stack pointer during its execution it must restore the stack pointer s original value before executing the final RTS of the called subroutine This restriction is required because a return a...

Page 53: ...xcept reset which wipes the slate clean and control is returned to D Bug12 a message is displayed explaining the reason for user program termination In addition D Bug12 disassembles the instruction at the current program counter PC address prints the CPU12 s register contents and waits for the next D Bug12 command to be entered by the user If a starting address is not supplied in the command line ...

Page 54: ... the current value of the program counter When user code reaches the temporary breakpoint and control is returned to D Bug12 a message is displayed explaining the reason for user program termination In addition D Bug12 disassembles the instruction at the current PC address prints the CPU12 s register contents and waits for a command to be entered by the user Restrictions None Example GT 820 Tempor...

Page 55: ...HELP Display this D Bug12 command summary LOAD AddressOffset Load S Records into memory MD StartAddress EndAddress Memory Display Bytes MDW StartAddress EndAddress Memory Display Words MM StartAddress Modify Memory Bytes CR Examine Modify next location or Examine Modify same location or Examine Modify previous location Exit Modify Memory command MMW StartAddress Modify Memory Words same subcommand...

Page 56: ...oaded into memory at a location other than that for which it was assembled During the loading process the S record data is not echoed to the control console However for each 10 S records that are successfully loaded an ASCII asterisk character is sent to the control console When an S record file has been loaded successfully control returns to the D Bug12 prompt The LOAD command is terminated when ...

Page 57: ...each line to display memory in the range of xxx0 through xxxF For example if 205 is entered as the start address and 217 as the ending address the actual memory range displayed would be 200 through 21F Restrictions None Example MD 800 0800 AA 04 37 6A 00 06 27 F9 35 AE 78 0D B7 56 78 20 7j 5 x Vx MD 800 87f 0800 AA 04 37 6A 00 06 27 F9 35 AE 78 0D B7 56 78 20 7j 5 x Vx 0810 B6 36 27 F9 35 AE 27 F9...

Page 58: ...f 16 minus 1 This causes each line to display memory in the range of xxx0 through xxxF For example if 205 is entered as the start address and 217 as the ending address the actual memory range displayed would be 200 through 21F Restrictions None Example MDW 800 0800 AA04 376A 0006 27F9 35AE 780D B756 7820 7j 5 x Vx MDW 800 87f 0800 AA04 376A 0006 27F9 35AE 780D B756 7820 7j 5 x Vx 0810 B636 27F9 35...

Page 59: ...ed for the modification and verification of memory contents These subcommands have this format Data CR Optionally update current location and display the next location Data or Optionally update current location and redisplay the current location Data or Optionally update current location and display the previous location Data Optionally update current location and exit MEMORY MODIFY With the excep...

Page 60: ...he modification and verification of memory contents These subcommands have this format Data CR Optionally update current location and display the next location Data or Optionally update current location and redisplay the current location Data or Optionally update current location and display the previous location Data Optionally update current location and exit MMW With the exception of the carria...

Page 61: ...bytes moved is one more than the EndAddress StartAddress The block of memory beginning at the destination address may overlap the memory block defined by the StartAddress and EndAddress One of the uses of the MOVE command might be to copy a program from RAM into the on chip EEPROM memory Restrictions A minimum of one byte may be moved if the StartAddress is equal to the EndAddress The maximum numb...

Page 62: ...previously entered breakpoints If the NOBR command is entered without any arguments all user breakpoints are removed from the breakpoint table Restrictions None Example BR 800 810 820 830 Breakpoints 0800 0810 0820 0830 NOBR 810 820 Breakpoints 0800 0830 NOBR All Breakpoints Removed Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com n...

Page 63: ...x RD The REGISTER DISPLAY command is used to display the CPU12 s registers Restrictions None Example RD PC SP X Y D A B CCR SXHI NZVC 0206 03FF 1000 3700 27 FF 1001 0001 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 64: ...ine When the last of the CPU12 s registers has been examined and or modified the RM command displays the first register giving the user an opportunity to make additional modifications to the CPU12 s register contents Typing a period as the first non space character on the line will exit the interactive mode of the register modify command and return to the D Bug12 prompt The registers are displayed...

Page 65: ...E and TBEQ NE that contain an offset that branches back to the instruction opcode do not execute The terminal appears to become stuck at the branch instruction and does not execute the instruction even if the condition for the branch instruction is satisfied This limitation can be overcome by using the GT GO TILL command to set a temporary breakpoint at the instruction following the branch instruc...

Page 66: ...X Y D A B CCR SXHI NZVC 0806 09FE 057C 0000 0F FF 1001 0000 0806 26FB BNE 0803 PC SP X Y D A B CCR SXHI NZVC 0803 09FE 057C 0000 0F FF 1001 0000 0803 830001 SUBD 0001 PC SP X Y D A B CCR SXHI NZVC 0806 09FE 057C 0000 0F FE 1001 0000 0806 26FB BNE 0803 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICON...

Page 67: ...E37B5302037FAFA5237B58A S1230480682037FAFA5637BD014037BC000095008A003C023D02377D0172B6EE37BD017259 S12304A037BC020095008A003C023D02377D018EB6EE27F937B0F50F379C37BC00CE27F901 S12304C000FC27F9104C27F90E68378000BE0A0D442D42756731362056312E3033202D20E3 S12304E04465627567204D6F6E69746F7220466F7220546865204D363848433136204661ED S12305006D696C790A0D2843292031393932204D6F746F726F6C612053656D69636F6E64BD S...

Page 68: ... control console for each 10 S records that are successfully verified When an S record file has been verified successfully control returns to the D Bug12 prompt If the contents of EVB memory do not match the corresponding data in the received S records an error message is displayed and the VERIFY command is terminated D Bug12 then returns to its command line prompt If the host computer continues t...

Page 69: ...Manual MOTOROLA Operation 69 Verify S Record File Against Memory Continued VERF Restrictions None Example VERF 1000 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 70: ...counter 0 to FFFF SP Stack pointer 0 to FFFF X X index register 0 to FFFF Y Y index register 0 to FFFF A A accumulator 0 to FF B B accumulator 0 to FF D D accumulator A B 0 to FFFF CCR Condition code register 0 to FF Table 3 4 Condition Code Register Bits CCR Bit Name Description Legal Values S STOP enable 0 or 1 H Half carry 0 or 1 N Negative flag 0 or 1 Z Zero flag 0 or 1 V Two s complement over...

Page 71: ...ion of a CPU register or CCR bit the entire CPU register set is displayed Restrictions None Example PC 700e PC SP X Y D A B CCR SXHI NZVC 700E 0A00 7315 7D62 47 44 1001 0000 X 1000 PC SP X Y D A B CCR SXHI NZVC 700E 0A00 1000 7D62 47 44 1001 0000 C 1 PC SP X Y D A B CCR SXHI NZVC 700E 0A00 1000 7D62 47 44 1001 0001 Z 1 PC SP X Y D A B CCR SXHI NZVC 700E 0A00 1000 7D62 47 44 1001 0101 D adf7 PC SP ...

Page 72: ...in execution from on chip EEPROM D Bug12 jumps to the starting EEPROM address before performing all of its initialization and is thus not operable Do not activate the program abort function under these conditions Instead move the jumper on header W20 to pins 2 and 3 and activate the reset function to return control to D Bug12 2 Terminate the user program with code that returns to D Bug12 after exe...

Page 73: ...t HEX file Appendix A S Record Format contains detailed information about the S record formats 4 Start the EVB with D Bug12 as the default operating mode using the procedure in 3 2 Startup 5 At the D Bug12 prompt issue D Bug12 s LOAD command with any parameters Note that this requires interaction with the terminal communications program s send file utility See Appendix B Communications Program Exa...

Page 74: ... on the stack and then decrements its stack pointer The 16 Kbytes of external RAM from 4000 to 7FFF are available for user code and data 3 9 2 Memory Map The information in Table 3 5 describes address ranges and locations Table 3 5 Factory Configuration Memory Map Address Range Description Location 0000 01FF CPU registers On chip MCU 0800 09FF 0A00 0BFF User code data Reserved for D Bug12 1 Kbyte ...

Page 75: ...ines perform specific functions If an application requires their use the EVB hardware and or operating software must be custom configured or special precautions must be taken in the application code to avoid conflicts with the D Bug12 usage PE0 XIRQ Program abort function S2 Additionally there are two software limitations on the program abort function D Bug12 enables the hardware XIRQ interrupt by...

Page 76: ... process incoming data at the selected baud rate The D Bug12 MD MDW T and HELP commands may be affected by this problem Sometimes the problem can be ignored without harm If it requires correcting try Using a slower baud rate A different communications program Closing unnecessary applications or exiting Windows In multitasking environments such as Windows and the Macintosh System 7 the problem can ...

Page 77: ...4 6 Microcontroller 84 4 7 Memory 86 4 7 1 Memory Types and Sockets 86 4 7 2 Chip Selects 88 4 7 3 Glue Logic 89 4 8 Clock Circuitry 90 4 9 Phase Locked Loop PLL 90 4 10 Reset 90 4 11 Low Voltage Inhibit LVI 91 4 12 Analog to Digital A D Converter 91 4 13 Background Debug Mode BDM Interface 91 4 14 Prototype Area 92 4 15 MCU Connectors 94 4 16 Schematics 99 Freescale Semiconductor I Freescale Semi...

Page 78: ...ion These headers are populated and the factory installed jumpers on them are preset for the default EVB hardware and firmware D Bug12 configurations Table 4 1 lists these headers by function and describes their default and optional jumper settings Cut trace header footprints offer EVB hardware options that are less likely to be changed These footprints are not populated The default connection bet...

Page 79: ...e Inhibit LVI 1 2 Off Low voltage inhibit is enabled Low voltage inhibit is disabled W3 RAM Write Protection 1 2 2 3 RAM write protection is disabled RAM write protection is enabled W10 TXD1 RS 232C Transmit Data TXD Enable SCI Port 1 1 2 2 3 TXD on SCI port 1 is enabled TXD on SCI port 1 is disabled 1 W12 and W13 together select the type of RAM installed 2 W22 W24 W29 W32 W33 and W36 together sel...

Page 80: ...8 pin package 1 2 3 4 5 6 Pin is connected to MCU address line A13 for narrow modes Pin is connected to MCU address line A14 for wide modes Pin is connected to VDD for the device s chip enable CE2 W14 SCI Port Assignment to Terminal Interface 1 2 2 3 SCI port 0 serves as the D Bug12 terminal interface SCI port 1 serves as the D Bug12 terminal interface Table 4 1 Jumper Selectable Functions Sheet 2...

Page 81: ...or narrow modes Pin is connected to MCU address line A18 for wide modes Pin is connected to VDD for 28 pin devices W29 2 ROM Pin Assignment Pin 29 of 32 pin package or pin 27 of 28 pin package 1 2 3 4 5 6 Pin is connected to MCU address line A14 for narrow modes Pin is connected to MCU address line A15 for wide modes Pin is connected to VDD to disable the device s write enable WE W30 3 MCU Backgro...

Page 82: ... PE6 MODB pin is connected to VSS MCU s PE6 MODB pin is connected to VDD W36 2 ROM Pin Assignment Pin 2 of 32 pin package 1 2 3 4 5 6 Pin is connected to MCU address line A16 for narrow modes Pin is connected to MCU address line A17 for wide modes Pin is connected to VDD W42 3 MCU MODA Select 1 2 2 3 MCU s PE5 MODA pin is connected to VSS MCU s PE5 MODA pin is connected to VDD Table 4 1 Jumper Sel...

Page 83: ...VDDI MCU core usage VSSEX0 VDDEX0 VSSEX1 VDDEX1 VSSEX2 VDDEX2 Three separate circuits for MCU I O pins VSSPLL VDDPLL Phase locked loop PLL VSSA VDDA VRL VRH A D converter power and reference voltages Refer to the EVB schematic diagrams 4 16 Schematics to locate the cut trace header footprint that isolates these circuits 4 5 Terminal Interface An RS 232C transceiver U5B links the MCU s two serial c...

Page 84: ...ing unit The programming model and stack frame are identical to those of the standard M68HC11 CPU The CPU12 instruction set is a proper superset of the M68HC11 instruction set All M68HC11 instruction mnemonics are accepted by CPU12 assemblers with no changes The EVB resident MC68HC812A4 U8 has seven modes of operation These modes are determined at reset by the state of three mode pins BKGD MODB an...

Page 85: ...mode is immediately active out of reset Execution begins from the background debug ROM Commands are sent to the CPU through the background debug interface pin A background debug interface is required as described in 4 13 Background Debug Mode BDM Interface For more information on the CPU refer to the CPU12 Reference Manual Motorola document order number CPU12RM AD Table 4 2 CPU Mode Selection BKGD...

Page 86: ...AM and ROM footprints support different memory device types SRAM EPROM and EEPROM and sizes 28 and 32 pin 8 to 512 Kbytes 300 or 600 mil spacing Figure 4 1 shows how the external memory sockets are used Table 3 5 Factory Configuration Memory Map depicts the EVB s default memory usage Note that the map is valid only for the factory supplied memory configuration NOTE The user available area in facto...

Page 87: ...ith sockets Two RAM and six ROM jumper headers allow configuration of the memory sockets for use with various types and sizes of memory These headers are preset for the factory supplied memories The default and optional settings are described in Table 4 1 Table 4 3 provides information about the supplied memories WIDE MODES NARROW MODES HIGH LOW 300 MIL 600 MIL 600 MIL 300 MIL ROM RAM Freescale Se...

Page 88: ...e illustration demonstrates the correct settings for CSP0 to serve as the ROM chip select and CSD to serve as the RAM chip select Figure 4 2 Chip Select Header Table 4 3 EVB Memories Supplied Type EPROM SRAM Manufacturer Atmel Corporation Dallas Semiconductor Corporation Part number AT27LV256R 20PC DS2064 Size 256 Kbits 32 K x 8 64 Kbits 8 K x 8 bits Package width 600 mil 600 mil Pin count 28 pin ...

Page 89: ...3 factory supplied or a PAL array U2 optional not populated to serve as the glue logic Figure 4 3 RAM ROM Logic Diagram shows the circuitry for the ROM and RAM logic Figure 4 3 RAM ROM Logic Diagram CS PAL ROM ONLY RAM ONLY LSTRB A0 LSB CS MSB CS CE OE ROM RAM WIDE LOW A1 A0 CE OE ROM RAM NARROW A0 A0 CE OE ROM RAM WIDE HIGH A0 A1 OR OR Freescale Semiconductor I Freescale Semiconductor Inc For Mor...

Page 90: ... changed 4 9 Phase Locked Loop PLL The PLL can be used to run the MCU on a timebase that differs from the clock frequency To alter the timebase capacitors must be installed between the MCU s XFC pin and the PLL s ground reference VSSPLL Connection points E4 E5 E6 E7 E8 and E9 provide space for these capacitors Header footprint W37 connects the XFC pin to the capacitors For more information refer t...

Page 91: ...available for A D usage in the factory default configuration The accuracy of the A D converter can be increased by supplying the MCU s A D circuitry with the same supply voltages used by the target hardware These supply lines VDDA and VSSA and the associated A D reference voltages VRH and VRL can be isolated from the EVB s power bus with cut trace footprints W15 W16 W17 and W18 Refer to the EVB sc...

Page 92: ...ts headers and device packages Figure 4 4 shows the component side view of the prototype area Ground VSS connections are provided along the three outboard peripheries with three loop style test points for connecting clips or probes Vdc VDD connections are provided along the inboard periphery Table 4 4 BDM Connector J5 Pin Assignments Pin Number Description 1 BKGD 2 VSS 3 No connection 4 RESET 5 No...

Page 93: ...93 Figure 4 4 Prototype Area Component Side View 79HOLES 20HOLES VdcBUS J8 J9 GNDBUS GNDtestpoints 79 HOLES J9 J8 20 HOLES Vdc BUS GND BUS GND TEST POINTS Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 94: ...e not directly connected to these headers due to impedance considerations Header footprints W37 W38 and W39 can be used to make these connections Figure 4 5 MCU Connector J8 Component Side View 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 PJ6 PJ4 PJ2 PJ0 VSSEX0 PG4 PG2 PG0 ...

Page 95: ...24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 VSSEX1 PA6 PA4 PA2 PA0 PF6 PF4 PF2 PF0 VSSAD PAD6 PAD4 PAD2 PAD0 VRL PH6 PH4 PH2 PH0 VSSEX2 PS6 PS4 PS2 PS0 PT6 PT4 PT2 PT0 VSS VSS VDDEX1 PA7 PA5 PA3 PA1 NC PF5 PF3 PF1 VDDAD PAD7 PAD5 PAD3 PAD1 VRH PH7 PH5 PH3 PH1 VDDEX2 PS7 PS5 PS3 PS1 PT7 PT5 PT3 PT1 VDD VDD Freescale Semiconductor I Freescale Semiconductor Inc For More Information On Th...

Page 96: ...ternal VSS and VDD connections for the MCU 19 BKGD BACKGROUND An I O line dedicated to the background debug function If it is a 0 out of reset then the MCU is in special mode This pin can be used for bidirectional communications with the MCU 20 NC Not connected 21 22 23 24 25 26 27 28 PC6 D14 D6 PC7 D15 D7 PC4D12 D4 PC5 D13 D5 PC2 D10 D2 PC3 D11 D3 PC0 D8 D0 PC1 D9 D1 PORT C bits 0 7 General purpo...

Page 97: ...pacitor connection for PLL circuit 49 50 VSSPLL VDDPLL VSSPLL VDDPLL VSS and VDD connections for the PLL circuit 51 XTAL CRYSTAL OUTPUT Crystal oscillator output 52 EXTAL EXTERNAL CLOCK INPUT Crystal oscillator input The frequency applied to this pin must be twice the desired bus speed 53 54 55 56 57 58 59 60 PB6 A6 PB7 A7 PB4 A4 PB5 A5 PB2 A2 PB3 A3 PB0 A0 PB1 A1 PORT B bits 0 7 General purpose I...

Page 98: ...S3 PF0 CS0 PF1 CS1 PORT F bits 0 5 General purpose I O port or chip selects 19 20 VSSAD VDDAD VSSAD VDDAD VSS and VDD connections for the MCU s A D converter 21 22 23 24 25 26 27 28 PAD6 PAD7 PAD4 PAD5 PAD2 PAD3 PAD0 PAD1 PORT AD A D converter channel or general purpose I O 29 30 VRL VRH VOLTAGE REFERENCE LOW and HIGH Reference voltages for the MCU s A D converter These can improve the accuracy of...

Page 99: ...pheral and serial communication interfaces The signal functions are serial clock slave select master in slave out master out slave in receiver data input and transmitter data out 49 50 51 52 53 54 55 56 PT6 IOC6 PT7 IOC7 PAIN PT4 IOC4 PT5 IOC5 PT2 IOC2 PT3 IOC3 PT0 IOC0 PT1 IOC1 PORT T bits 0 7 General purpose I O or timer lines 57 58 59 60 VSS VDD VSS VDD VSS VDD EVB system return VSS and power V...

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Page 117: ...cters 122 A 2 Overview The Motorola S record format was devised to encode programs or data files in a printable format for transport between computer platforms The format also provides for editing of the S records and monitoring the cross platform transfer process A 3 S Record Contents Each S record is a character string composed of several fields which identify Record type Record length Memory ad...

Page 118: ...ecord Fields Type Record Length Address Code Data Checksum Table A 2 S Record Field Contents Field Printable Characters Contents Type 2 S record type S0 S1 etc Record Length 2 Character pair count in the record excluding the type and record length Address 4 6 or 8 2 3 or 4 byte address at which the data field is to be loaded into memory Code Data 0 2n From 0 to n bytes of executable code memory lo...

Page 119: ...ecord format may contain the record types listed in Table A 3 Only one termination record is used for each block of S records Normally only one header record is used although it is possible for multiple header records to occur Table A 3 S Record Types Type Description S0 Header record for each block of S records The code data field may contain any descriptive information identifying the following ...

Page 120: ...008237C2A S11300100002000800082529001853812341001813 S113002041E900084 42234300182342000824A952 S107003000144ED492 S9030000FC In the example the format consists of An S0 header Four S1 code data records An S9 termination record A 6 1 S0 Header Record The S0 header record is described in Table A 4 Table A 4 S0 Header Record Field S Record Entry Description Type S0 S record type S0 indicating a head...

Page 121: ... Entry Description Type S1 S record type S1 indicating a code data record to be loaded verified at a 2 byte address Record Length 13 Hexadecimal 13 decimal 19 indicating 19 character pairs representing 19 bytes of binary data follow Address 0000 4 character 2 byte address field hexadecimal address 0000 indicates location where the following data is to be loaded Code Data Opcode Instruction 28 24 2...

Page 122: ...rocessor based system For example the first S1 record in Table A 5 is sent as shown here Table A 6 S9 Header Record Field S Record Entry Description Type S9 S record type S9 indicating a termination record Record Length 03 Hexadecimal 04 indicating three character pairs three bytes follow Address 00 00 4 character 2 byte address field zeroes Code Data There is no code data in an S9 record Checksum...

Page 123: ...t for DOS IBM PC 126 B 4 1 Setup 126 B 4 2 S Record Transfers to EVB Memory 127 B 5 Kermit Sun Workstation 127 B 5 1 Setup 127 B 5 2 S Record Transfers to EVB Memory 128 B 6 MacTerminal Apple Macintosh 128 B 6 1 Setup 128 B 6 2 S Record Transfers to EVB Memory 129 B 7 Red Ryder Apple Macintosh 130 B 7 1 Setup 130 B 7 2 S Record Transfers to EVB Memory 130 Freescale Semiconductor I Freescale Semico...

Page 124: ...it is not feasible to document all of the communications programs that are available or to guarantee that a newer revision of a program behaves in exactly the same way as the version used to develop the procedure For this reason the steps are as generic as possible in their descriptions They can thus serve as guidelines for programs not exemplified in this manual Always consult the documentation f...

Page 125: ...es YES Pace character 0 ASCII Character pacing 25 1 1000th sec Line pacing 10 1 10th sec CR translation NONE LF translation NONE 5 Enter the Line Settings menu by pressing ALT P Select baud rate 9600 or the customized EVB setting data bits 8 stop bits 1 parity none COM port Host port used as the EVB terminal interface 6 Reset the EVB by pressing S1 or by activating the appropriate custom reset cir...

Page 126: ...letion of the S record file transfer the D Bug12 prompt is displayed B 4 Kermit for DOS IBM PC B 4 1 Setup To set up Kermit using DOS on an IBM compatible PC for use as the EVB terminal first refer to section 3 2 Startup for the EVB startup procedure which is inter related with this example Then follow these steps 1 At the DOS prompt invoke Kermit by typing kermit ENTER 2 Set the baud rate to 9600...

Page 127: ...d B 5 Kermit Sun Workstation B 5 1 Setup To set up Kermit on the Sun Workstation for use as the EVB terminal first refer to section 3 2 Startup for the EVB startup procedure which is inter related with this example Then follow these steps 1 In a shell window invoke Kermit by typing kermit ENTER 2 Set the serial port to the one in use for the EVB ttya ttyb etc by typing set line dev ttya ENTER 3 Se...

Page 128: ... window type cat filename dev ttya ENTER Upon completion of the S record file transfer the D Bug12 prompt is displayed in the shell window being used for the EVB terminal interface B 6 MacTerminal Apple Macintosh Using MacTerminal on an Apple Macintosh computer is described here B 6 1 Setup To set up MacTerminal on an Apple Macintosh computer for use as the EVB terminal first refer to 3 2 Startup ...

Page 129: ...sfers to EVB Memory To load an S record file from the host computer into EVB memory using MacTerminal first verify that the host is correctly configured and operating as the EVB terminal Then follow these steps 1 At the D Bug12 prompt enter the LOAD or VERF command with any parameters 2 From the Macintosh File menu select Send File ASCII 3 From the dialog box select the S record file to be transfe...

Page 130: ...D Bug12 prompt should appear on the display Continue with the startup procedure in 3 2 Startup B 7 2 S Record Transfers to EVB Memory To load an S record file from the host computer into EVB memory using Red Ryder first verify that the host is correctly configured and operating as the EVB terminal Then follow these steps 1 At the D Bug12 prompt enter the LOAD or VERF command with any parameters 2 ...

Page 131: ...d of the code listed here opt lis assembler directive to turn listing on 0A00 MonRAMStart equ 0A00 0200 MonRAMSize equ 0200 0800 RAM_START equ 0800 0400 RAMSize equ 0400 0C00 STACKTOP equ RAM_START RAMSize stack at top of int RAM 1000 EE_START equ 1000 4K EEPROM located here out of reset in expanded modes FD80 org fd80 INITIALIZATION Initialization code for the M68HC12A4EVB D Bug12 monitor program...

Page 132: ... CRx bits are write once in normal modes COPCTL CME FCME FCM FCOP DISR CR2 CR1 CR0 16 FDA1 790016 clr COPCTL disable watchdog Enable Program chip select 0 and Data chip select CSCTL0 20 after reset CSP0 on others off also set data chip select to cover 0000 7FFF will mirror to fill space internal resources have higher priority in case of overlaps CSCTL0 0 CSP1E CSP0E CSDE CS3E CS2E CS1E CS0E 3C CSC...

Page 133: ...n 8 00 MHz E clock 2 Subroutine located in external EPROM selected by CSP0 3 CSP0 programmed for 1 E clock stretch This routine is called by D Bug12 s WriteEEByte function through a pointer stored in the Customization Data Table FDBE _EEDelay FDBE CE2710 ldx 10000 load delay count into x FDC1 09 DlyLoop dex decrement count FDC2 26FD bne DlyLoop loop till done FDC4 3D rts return Freescale Semicondu...

Page 134: ...uation Board Rev 1 134 D Bug12 Startup Code MOTOROLA D Bug12 Startup Code Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 135: ...M Erase Program Delay Function Pointer Field 138 D 2 9 Auxiliary Command Table Entries 138 D 2 Customization Data Area The customization data area located in EPROM from FE80 to FEFF allows users to change default data parameters used by D Bug12 The data contained in this area is described by C data structure The CustomData typedef is shown here For those unfamiliar with C an assembly language equi...

Page 136: ...Y index register UserPC dc w 0000 User CPU Program Counter UserSP dc w 0A00 User CPU Stack Pointer SysClk dc l 8000000 System Clock frequency in Hz IOBase dc w 0000 Base address of the I O registers SCIBaudRegVal dc w 52 Initial SCI BAUD register value EEBase dc w 1000 Base address of the on chip EEPROM EESize dc w 4096 Size of the on chip EEPROM EEDelay dc w _EEDELAY Address of EEPROM program era...

Page 137: ...herefore the IOBase entry should be only a multiple of 2048 The value of IOBase is set to 0x0000 which is the default address of the I O registers for the MC68HC812A4 NOTE It is the responsibility of the startup code to set the base address of the I O registers D Bug12 does not set or change the I O register base address D 2 6 SCIBaudRegVal Field The SCIBaudRegVal field is used to set the initial ...

Page 138: ...se address of the on chip EEPROM for the MC68HC812A4 The value of EESize is also set to 0x1000 4096 which is the size of the on chip EEPROM Setting the value of EESize to 0 disables the WriteMem function s ability to write to on chip EEPROM NOTE It is the responsibility of the startup code to set the base address of the EEPROM D Bug12 does not set or change the EEPROM base address D 2 8 EEPROM Era...

Page 139: ...ction parameter is a pointer to an array of char Each char points to one of the command line parameters parsed by the command line interpreter The function implementing the new command can report any error conditions to the user in one of two ways If the error condition can be described by one of the error messages in the enumerated constant list here the user defined command should return the app...

Page 140: ... Board Rev 1 140 D Bug12 Customization Data MOTOROLA D Bug12 Customization Data Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 141: ...her EVB operating firmware the factory programming must be retained and burned into the custom chips along with the custom code Table E 1 maps the EVB s logical addresses from Table 3 5 Factory Configuration Memory Map to the pin level physical addresses of U7 and U9A Note that the lower half of each EPROM from 0000 to 3FFF is unused and is filled with 1s This is necessary because of the chip sele...

Page 142: ...n addresses Factory or modified 7EC0 7EFF FD81 FDFF odd addresses Factory or modified 7EC0 7EFF FE00 FE7E even addresses Factory 7F00 7F3F FE01 FE7F odd addresses Factory 7F00 7F3F FE80 FEFE even addresses Factory or modified 7F40 7F7F FE81 FEFF odd addresses Factory or modified 7F40 7F7F FF00 FFBE even addresses Custom 7F80 7FBF FF01 FFBF odd addresses Custom 7F80 7FBF FFC0 FFFE even addresses Fa...

Page 143: ...n chip EEPROM from F000 the default in special single chip mode to 1000 To do this change the data at address 0012 to a value of 11 using the appropriate debugging tool For MCUdebug the correct command is MM 12 11 NOTE Step 6 must be repeated each time the EVB is reset in this mode as the EEPROM s base address defaults to F000 at reset Table 4 1 Jumper Selectable Functions provides full descriptio...

Page 144: ...ion For information on using the SDI refer to the Serial Debug Interface User s Manual Motorola document order number SDIUM D Table F 1 SDI Memory Map Address Range Description Location 0000 01FF CPU registers On chip MCU 0800 0BFF User data area 1 Kbyte on chip RAM MCU 1000 1FFF User code area 4 Kbyte on chip EEPROM MCU C000 FFFF User code data area 16 Kbyte external RAM U4 U6A Freescale Semicond...

Page 145: ...ican Standard Code for Information Interchange A widely accepted correlation between alphabetic and numeric characters and specific 7 bit binary numbers breakpoint During debugging of a program it is useful to run instructions until the CPU gets to a specific place in the program and then enter a debugger program A breakpoint is established at the desired address by temporarily substituting a soft...

Page 146: ...from a memory location to a CPU development tools Software or hardware devices used to develop computer programs and application hardware Examples of software development tools include text editors assemblers debug monitors and simulators Examples of hardware development tools include simulators logic analyzers and PROM programmers EPROM Erasable programmable read only memory A non volatile type o...

Page 147: ...rogram An object code file can be used to load binary information into a computer system Motorola uses the S record file format for object code files operand An input value to a logical or mathematical operation opcode A binary code that instructs the CPU to do a specific operation in a specific way OTPROM A non volatile type of memory that can be programmed but cannot be erased An OTPROM is an EP...

Page 148: ... See source program source program A text file containing instruction mnemonics labels comments and assembler directives The source file is processed by an assembler to produce a composite listing and an object file representation of the program stack pointer A CPU register that holds the address of the next available storage location on the stack TTL Transistor to transistor logic VDD The positiv...

Page 149: ...s 122 ASM command 44 45 46 47 B background debug mode BDM as user interface 21 22 30 interface connector J5 91 MCU mode 65 85 BAUD command 48 BF command 49 block diagram EVB system 19 BR command 50 BULK command 51 C CALL command 52 checksum 117 chip select 88 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE ...

Page 150: ...nds RegisterName 70 71 ASM 44 45 46 47 BAUD 48 BF 49 BR 50 BULK 51 CALL 52 G 53 GT 54 HELP 55 LOAD 56 MD 57 MDW 58 MM 59 MMW 60 MOVE 61 NOBR 62 RD 63 RM 64 T 65 66 UPLOAD 67 VERF 68 69 communications EVB host baud rate 32 48 49 limitations 76 parameters 31 SCI ports 29 84 software 22 31 124 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freesca...

Page 151: ...rs 15 type 15 crystal 90 D D Bug12 aborting a user program 40 command set 42 command line format 40 configuration requirements 20 21 28 30 78 141 customization data 135 description 20 22 generating user code 21 73 limitations imposed by 22 75 memory usage 74 141 resetting 39 stack pointer 74 starting 38 startup code 131 startup modes 22 28 38 72 terminal interface 21 83 D Bug12 XE 24 43 DS1 83 Fre...

Page 152: ...78 features 15 firmware 20 functional overview 20 operating instructions 38 packing list 27 restrictions on use 75 specifications 23 unpacking 27 examples S records 120 F file transfers 56 73 124 firmware 20 G G command 53 GT command 54 H headers connector 78 cut trace 78 description 78 jumper 78 HELP command 55 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Pro...

Page 153: ... 83 LOAD command 56 low voltage inhibit LVI 91 M M68HC12A4EVB evaluation board 15 MC68HC812A4 microcontroller unit 15 MCU access interface 21 92 94 description 84 isolatable power circuits 83 location 18 modes 84 85 86 87 restrictions on use 22 74 75 socket 28 type 23 84 MD command 57 MDW command 58 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to ww...

Page 154: ...ocations 18 19 map EPROM 142 map factory default 73 74 map SDI configuration 144 on chip 84 144 programming 22 RAM 20 32 86 ROM 86 sockets 86 87 speed enhancement 20 32 SRAM 20 32 86 usage 73 86 wait states 20 32 88 microcontroller unit 15 MM command 59 MMW command 60 monitor program 20 MOVE command 61 multiple serial interface MSI 99 N NOBR command 62 O oscillator 90 Freescale Semiconductor I Fre...

Page 155: ...irements 22 23 printed circuit board description 78 program abort 21 39 40 53 72 75 prototype area 21 92 R RAM 20 RD command 63 record length 117 record type 117 registers 33 40 50 53 54 63 64 65 74 75 84 135 144 reset 21 28 32 38 39 84 90 RM command 64 ROM 20 S S records 56 67 68 69 70 71 73 117 122 S1 S2 21 schematics 99 116 SCI ports baud rate 48 configuration 29 84 limitations 75 usage 21 22 2...

Page 156: ...ds 118 overview 117 S0 header record 120 S0 record 120 S1 record 121 S9 record 122 termination record 122 switches 21 locations 18 S1 reset 39 S2 program abort 40 T T command 65 66 terminal baud rate 32 48 cabling 30 communications parameters 31 communications software 22 31 124 connectors 29 83 interface circuitry 83 limitations 76 requirements 22 SCI ports 21 29 83 setup 29 31 83 Freescale Semic...

Page 157: ...7 92 timebase 90 U upacking instructions 27 UPLOAD command 67 V vector memory area 74 144 VERF command 68 69 W wait states 20 32 88 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 158: ...8HC12A4EVB Evaluation Board Rev 1 158 Index MOTOROLA Index Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 159: ...Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 160: ...ducts for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim all...

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