M54455EVB User’s Manual, Rev. 4
Freescale Semiconductor
31
4.14.3.2
CPLD Control Register (CPLD_CONTROL)
Following reset, PHY0_PWRDN, ATA_ENABLE, and ULPI_RESET pins are set according to the
CPLD_MODE switch (SW1) settings. The CPLD_CONTROL register allows you to override these
switch settings.
4.14.3.3
CPLD On-Die Termination Register (CPLD_SDODT)
CPLD_SDODT controls the DDR SDRAM on-die termination pins.
Address: 0x0800_0001 (CPLD_CONTROL)
7
6
5
4
3
2
1
0
R
0
0
0
0
0
FEC0
ATA
ULPI
W
Reset:
0
0
0
0
0
—
—
—
Figure 20. CPLD_CONTROL Register
Table 29. CPLD_CONTROL Field Descriptions
Field
Description
7–3
Reserved, must be cleared.
2
FEC0
FEC0 PHY mode
0
FEC0 Ethernet PHY in normal/functional mode
1
FEC0 Ethernet PHY in power down mode
1
ATA
ATA and FEC1 PHY mode
0
Full ATA data bus enabled/FEC1 PHY in power down mode
1
Upper 8-bits of ATA data bus disabled; FEC1 PHY in normal/functional mode
0
ULPI
ULPI PHY mode
0
ULPI PHY in normal/functional mode
1
ULPI PHY held in reset state
Address: 0x0800_0002 (CPLD_SDODT)
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
ODT
W
Reset:
0
0
0
0
0
0
0
0
Figure 21. CPLD_SDODT Register
Table 30. CPLD_SDODT Field Descriptions
Field
Description
7–2
Reserved, must be cleared.
1–0
ODT
Control state of the corresponding DDR SDRAM on-die termination pins. These pins are for test purposes only. The
M54455EVB provides external parallel termination for the DDR2 interface.