Freescale Semiconductor DSPD56362EVM, Upgrade Manual

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68HC11 SOURCE CODE DESCIPTION
SYSTEM-SPECIFIC CONFIGURATION
MOTOROLA DSPD56362EVM Upgrade Manual 3-3
ENHANCED
SERIAL
AUDIO
INTERFACE SAICR 0xFFFFB4 0x000000 Independent clock and frame sync signals for
Rx and Tx (asynchronous)
RCR 0xFFFFB7 0x714902 RX1 is enabled, shift data in MSB first,
left-aligned data word, network mode, 32-bit
slot length, 16-bit word length, word-lenght
frame sync, frame sync occurs 1 serial clock
cycle earlier, Rx, Rx exception, and Rx even
data slot interrupts are enabled
RCCR 0xFFFFB8 0x0C0200 Fixed divide by 8 prescaler is operational, 2
words per frame, falling edge of Rx clock is
used to clock data in and frame sync, rising
edge of Rx clock is used to latch data in and
frame sync, frame start indicated by low level
on frame sync pin
TCR 0xFFFFB5 0x717D0F TX0, TX1, TX2 and TX3 are enabled, shift
data out in MSB first, left-aligned data word,
network mode, 32-bit slot length, 24-bit word
length, word-length frame sync, Tx, Tx
exception, and Tx even data slot interrupts are
enabled
TCCR 0xFFFFB6 0x0C0200 Fixed divide by 8 prescaler is operational, 2
words per frame, falling edge of Tx clock is
used to clock data out and frame sync, rising
edge of Rx clock is used to latch the data and
frame sync in, frame start is indicated by low
level on frame sync pin
RSMA 0xFFFFBB 0x000003 Receive a data word and generate a receive
full condition RDF=1 for slots 1 and 2
RSMB 0xFFFFBC 0x000000 Only slots 1 and 2 are used
TSMA 0xFFFFB9 0x000003 Transmit a data word and generate a transmit
empty condition TDE=1 for slots 1 and 2
TSMB 0xFFFFBA 0x000000 Only slots 1 and 2 are used
Table 3-1 InitAV2 Default Settings (Continued)
REGISTER ADDRESS VALUE DESCRIPTION
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