FII-PRA006/010 Hardware Reference Guide
Fraser Innovation Inc
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The development board reserves two GPIO interfaces, P1 and P2. The P1
interface contains 6 standard IO pin PFGA resources, 2 GND signals, and 2
adjustable power signals. The P2 interface contains 3 pairs of LVDS signals, which
can also be used as 6 standard IOs; 1 pair of clock signals can be used as ordinary
clocks or LVDS clocks, or 2 standard IO or 1 pair LVDS signals; 2 GND Signal, and 2
adjustable power signals. The schematics is as follows:
Figure 13.1 Schematics of GPIO
Figure 13.2 GPIO Physical Picture
GPIO pin assignment