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Forlinx SBC OKMX8MPQ-C, User Manual

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Forlinx SBC OKMX8MPQ-C User Manual Download Page 21

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Table 7 RIGHT_DOWN (P4) (odd)

Num

Ball

Signal

GPIO

Vol

Spec.

Default function

RD_1

—

GND

—

—

GN
D

GND

RD_3

D22

CSI1_CKP

—

—

CSI1 clock+

CSI1_CKP

RD_5

E22

CSI1_CKN

—

—

CSI1 clock-

CSI1_CKN

RD_7

—

GND

—

—

GN
D

GND

RD_9

E18

CSI1_DN0

—

—

CSI1 data 0-

CSI1_DN0

RD_11

D18

CSI1_DP0

—

—

CSI1 data 0+

CSI1_DP0

RD_13

—

GND

—

—

GN
D

GND

RD_15

E20

CSI1_DN1

—

—

CSI1 data 1-

CSI1_DN1

RD_17

D20

CSI1_DP1

—

—

CSI1 data 1+

CSI1_DP1

RD_19

—

GND

—

—

GN
D

GND

RD_21

E24

CSI1_DN2

—

—

CSI1 data 2-

CSI1_DN2

RD_23

D24

CSI1_DP2

—

—

CSI1 data 2+

CSI1_DP2

RD_25

—

GND

—

—

GN
D

GND

RD_27

E26

CSI1_DN3

—

—

CSI1 data 3-

CSI1_DN3

RD_29

D26

CSI1_DP3

—

—

CSI1 data 3+

CSI1_DP3

RD_31

—

GND

—

—

GN
D

GND

RD_33

B21

CSI2_DN3

—

—

CSI2 data 3-

CSI2_DN3

RD_35

A21

CSI2_DP3

—

—

CSI2 data 3+

CSI2_DP3

RD_37

—

GND

—

—

GN
D

GND

RD_39

B22

CSI2_DN2

—

—

CSI2 data 2-

CSI2_DN2

RD_41

A22

CSI2_DP2

—

—

CSI2 data 2+

CSI2_DP2

RD_43

—

GND

—

—

GN
D

GND

RD_45

B24

CSI2_DN1

—

—

CSI2 data 1-

CSI2_DN1

RD_47

A24

CSI2_DP1

—

—

CSI2 data 1+

CSI2_DP1

RD_49

—

GND

—

—

GN
D

GND

RD_51

B25

CSI2_DN0

—

—

CSI2 data 0-

CSI2_DN0

RD_53

A25

CSI2_DP0

—

—

CSI2 data 0+

CSI2_DP0

RD_55

—

GND

—

—

GN
D

GND

RD_57

B23

CSI2_CKN

—

—

CSI2 clock-

CSI2_CKN

RD_59

A23

CSI2_CKP

—

—

CSI2 clock+

CSI2_CKP

RD_61

—

GND

—

—

GN
D

GND

RD_63

—

NVCC_SNVS_1

—

1.8V

SoM SNVS voltage

NVCC_SNVS_1

RD_65

—

GND

—

—

GN
D

GND

RD_67

—

GND

—

—

GN
D

GND

RD_69

—

GND

—

—

GN
D

GND

RD_71

—

GND

—

—

GN
D

GND

RD_73

—

VSYS_5V

—

5V

SoM main power input 5V

VSYS_5V

RD_75

—

VSYS_5V

—

5V

SoM main power input 5V

VSYS_5V

RD_77

—

VSYS_5V

—

5V

SoM main power input 5V

VSYS_5V

RD_79

—

VSYS_5V

—

5V

SoM main power input 5V

VSYS_5V

Summary of Contents for SBC OKMX8MPQ-C

Page 1: ...1 1 SoM FETMX8MPQ C SBC OKMX8MPQ C ARM Cortex A53 Cortex M7 Embedded Development Platform Hardware Manual Rev 2 0 Forlinx Embedded Technology Co Ltd www forlix net User s Manual...

Page 2: ...untidy conditions Please do not use or store the product in alternate cold and hot conditions to avoid condensing which will damage components Please do not treat the product rudely Any falling off kn...

Page 3: ...3 3 Copyright Announcement Please note that reproduction of this User Manual in whole or in part without express written permission from Forlinx is not permitted...

Page 4: ...0 Carrier board PCB version updated to V2 0 1 PHY chip changed from AR8031 AL18 to YT8521 2 Power circuited controlled by MOS added with RC to avoid previous power drops during powering including VSYS...

Page 5: ...to help users to solve the problems 3 Accesses to Technical Support 3 1 If you are able to understand Chinese you can try to all the technical persons directly the tel number non instant messenger is...

Page 6: ...TMX8MM C Pin Spec 23 2 6 1 Power Pins 23 2 6 2 Reset Control Pin 23 2 6 3 Boot Pin 23 2 6 4 Function Control Pin 23 2 6 5 USB 24 2 6 6 SPI 24 2 6 7 SAI 24 2 6 8 UART 25 2 6 9 IIC 25 2 6 10 JTAG 26 2 6...

Page 7: ...MIPI DSI 42 3 4 13 LVDS 42 3 4 14 HDMI 43 3 4 15 Audio 43 3 4 16 4G 5G 44 3 4 17 WIFI BT 45 3 4 18 PCIe 46 3 4 19 USB Host 47 3 4 20 USB3 0 Type C 48 3 4 21 Ethernet 50 3 4 22 LED 52 3 4 23 RTC 52 App...

Page 8: ...ocessor audio digital signal processor machine learning and graphics accelerators The i MX 8M Plus provides additional computing resources and peripherals Advanced security modules for secure boot cip...

Page 9: ...NKZAB i MX 8M PlusDual NPU ISP VPU HiFi 4 CAN FD 2 1 6 GHz Industrial MIMX8ML8DVNLZAB i MX 8M PlusQuad NPU ISP VPU HiFi 4 CAN 4 1 8 GHz Consumer MIMX8ML6DVNLZAB i MX 8M PlusQuad ISP VPU CAN 4 1 8 GHz...

Page 10: ...10 10 Chapter 2 Introduction of SoM FETMX8MPQ C 2 1 Exterior of SoM FETMX8MPQ C FETMX8MPQ C Note FETMX8MPX C is available for multiple processors so it s printed as FETMX8MPX C 2 2 Dimension Drawing...

Page 11: ...ead size Hole depth 0 1 0 08 Name NO Length L 0 1 Interval height code Minimum thick A maximum C maximum E 0 1 Pore 0 08 Minimum Bonding pad 1 8 2 5 3 5 M2 0 4 through hole smtsob M2 2 3 4 6 1 53 1 53...

Page 12: ...d 1 5Mbit s Device mode SS HS FS PCIe 1 PCI Express Gen3 MIPI_CSI 2 Two 4 lane MIPI CSI up to 1 5Gbps MIPI_DSI 1 One 4 lane MIPI DSI up to 1 5Gbps 1080 p60 WUXGA 1920x1200 at 60 Hz 1920x1440 at 60 Hz...

Page 13: ...omply with CAN FD protocol and also CAN2 0B SAI 6 Available for IIS AC97 TDM and Codec DSP SPDIF 1 S PDIF PWM 4 16 bit upcounter JTAG 1 2x 5 pitch of 2 0mm headers QSPI 1 Used by SoM connected to 16MB...

Page 14: ...14 14...

Page 15: ..._SCL LU_13 AD8 I2C4_SDA GPIO5_IO21 3 3V I2C4 data I2C4_SDA LU_15 GND GND GND LU_17 AH6 I2C2_SCL GPIO5_IO16 3 3V I2C2 clock I2C2_SCL LU_19 AE8 I2C2_SDA GPIO5_IO17 3 3V I2C2 data I2C2_SDA LU_21 AJ6 I2C3...

Page 16: ...tion LU_2 GND GND GND LU_4 AJ3 UART1_TXD GPIO5_IO23 3 3V UART1 data sending UART1_TXD LU_6 AD6 UART1_RXD GPIO5_IO22 3 3V UART1 data receiving UART1_RXD LU_8 GND GND GND LU_10 AH5 UART4_TXD GPIO5_IO29...

Page 17: ...IO1_IO05 GPIO1_IO5 3 3V GPIO CSI1_SYNC3 3 RU_19 A4 GPIO1_IO14 GPIO1_IO14 3 3V GPIO TYPEC_HOST_ RU_21 B5 GPIO1_IO15 GPIO1_IO15 3 3V GPIO CSI_MCLK3 3 RU_23 A8 GPIO1_IO08 GPIO1_IO8 3 3V GPIO PCIE_RST RU_...

Page 18: ...RU_20 GND GND GND RU_22 D14 USB2_DP USB2 data USB2_DP RU_24 E14 USB2_DN USB2 data USB2_DN RU_26 GND GND GND RU_28 B13 USB2_TXN USB2 send USB2_TXN RU_30 A13 USB2_TXP USB2 send USB2_TXP RU_32 GND GND G...

Page 19: ...GND GND LD_39 AJ27 HDMI_TXN2 HDMI differential data 2 HDMI_TXN2 LD_41 AH27 HDMI_TXP2 HDMI differential data 2 HDMI_TXP2 LD_43 GND GND GND LD_45 AH28 ENET_MDC GPIO1_IO16 1 8V ENET serial management cl...

Page 20: ...IO2_IO14 1 8 3 3 SD2 command signal SD2_CMD LD_38 AB29 SD2_CLK GPIO2_IO13 1 8 3 3 SD2 clock SD2_CLK LD_40 AC28 SD2_DATA0 GPIO2_IO15 1 8 3 3 SD2 data bit 0 SD2_DATA0 LD_42 AC29 SD2_DATA1 GPIO2_IO16 1 8...

Page 21: ...DN3 CSI2 data 3 CSI2_DN3 RD_35 A21 CSI2_DP3 CSI2 data 3 CSI2_DP3 RD_37 GND GN D GND RD_39 B22 CSI2_DN2 CSI2 data 2 CSI2_DN2 RD_41 A22 CSI2_DP2 CSI2 data 2 CSI2_DP2 RD_43 GND GN D GND RD_45 B24 CSI2_DN...

Page 22: ...ta 3 LVDS0_TX3_ RD_36 J28 LVDS0_TX3_N LVDS0 data 3 LVDS0_TX3_ RD_38 GN GND GND RD_40 D29 LVDS0_CLK_P LVDS0 clock LVDS0_CLK_ RD_42 G28 LVDS0_CLK_N LVDS0 clock LVDS0_CLK_ RD_44 GN GND GND RD_46 G29 LVDS...

Page 23: ...SoM power ground all GND pins should be circuited 2 6 2 Reset Control Pin Pin Signal I O Default function Pin NO SoM reset SYS_nRST I SoM power off and reset low voltage valid RU_77 CPU reset POR_B I...

Page 24: ...ck LD_16 ECSPI1_MOSI O ECSPI1 host output slave input LD_18 SPI2 ECSPI2_SCLK O ECSPI2 clock LD_22 ECSPI2_SS0 O ECSPI2 chip select LD_24 ECSPI2_MOSI O ECSPI2 host output slave input LD_26 ECSPI2_MISO I...

Page 25: ...ata LU_62 SAI5 SAI5_RXFS I SAI5 receive frame sync LU_16 SAI5_RXC I SAI5 receive bit clock LU_18 SAI5_RXD2 I SAI5 receive data 2 LU_20 SAI5_RXD1 I SAI5 receive data 1 LU_22 SAI5_RXD3 I SAI5 receive da...

Page 26: ...O RGMII send control LD_61 ENET_RXC I RGMII receive clock LD_65 ENET_RX_CTL I RGMII receive control LD_67 ENET_RD0 I RGMII receive data 0 LD_71 ENET_RD1 I RGMII receive data 1 LD_73 ENET_RD2 I RGMII r...

Page 27: ..._33 CSI2_DP3 I CSI2 data 3 RD_35 CSI2_DN2 I CSI2 data 2 RD_39 CSI2_DP2 I CSI2 data 2 RD_41 CSI2_DN1 I CSI2 data 1 RD_45 CSI2_DP1 I CSI2 data 1 RD_47 CSI2_DN0 I CSI2 data 0 RD_51 CSI2_DP0 I CSI2 data 0...

Page 28: ...0 RD_60 2 6 15 PCIe Peripheral Signal I O Default function Pin No PCIE1 PCIE_RXN I PCIE data receiving RU_34 PCIE_RXP I PCIE data receiving RU_36 PCIE_TXN O PCIE data sending RU_40 PCIE_TXP O PCIE dat...

Page 29: ...I O SD2 command signal LD_36 SD2_CLK O SD2 clock LD_38 SD2_DATA0 I O SD2 data bit 0 LD_40 SD2_DATA1 I O SD2 data bit 1 LD_42 SD2_RESET_B O SD2 reset signal LD_44 SD2_NCD I SD2 card detect signal LD_46...

Page 30: ...schematic please refer to Appendix4 except minimum system we kindly suggest users to mount some peripherals such as debug port to check serial output information preserve OTG for firmware installation...

Page 31: ...8MPQ C Carrier Board Features 3 1 Overview of OKMX8MPQ C OKMX8MPQ C single board computer consists of carrier board and SoM the SoM can connect with carrier board by three ultra thin connectors 3 2 OK...

Page 32: ...by Forlinx is 38mm 38mm 23mm picture is as below 3 3 Carrier Board Features Peripheral QTY Spec USB3 0 Type C 1 USB3 0 Type C available for DFP UFP and DRP USB3 0 2 USB Type A header only for Host MIP...

Page 33: ...l transceiving direction KEY 4 Power on off reset keys and extra 2 for users definition LED 2 for users definition red and green DEBUG UART 2 3 5 pin header with pitch of 2 0mm integrated to USB Type...

Page 34: ...34 34...

Page 35: ...3 4 3 Boot There are 4 DIP switches S1 for booting mode selection Boot mode DIP Internal fuses Serial downloader EMMC SD QSPI MODE3 OFF OFF OFF OFF OFF MODE2 OFF OFF OFF OFF ON MODE1 OFF OFF ON ON ON...

Page 36: ...www wch cn products CH342 html Then take USB to Type C cable to connect development board P11 to USB port on PC and in computer device management it will generate 2 COM ports A port is for A53 debug a...

Page 37: ...37 37 3 4 5 General UART There are 4 general serial ports on carrier board rate up to 12Mbps designed as 2 5pin 2 0mm simple horn seat...

Page 38: ...rts are available on carrier board comply with CAN FD designed with 1500VDC electrical isolation and ESD4 solution The headers are from P29 and we kindly suggest users to take it common grounded when...

Page 39: ...al isolation and ESD4 solution MAX13487 can control transceiving direction automatically P28 is short circuit jumper for 120 resistor of AB wire and we kindly suggest users to take it common grounded...

Page 40: ...i MX8M Plus Boundary Scan mode 3 5 10 TF card SD2 of CPU is for TF card can support HS I TF card rate up to 104MB s TF card power supply VSD_3V3 is from the SoM power supply current is 400mA Note 1 bu...

Page 41: ...IPI CSI can be mounted with OV5645 camera module up to 2592x1944 15fps All CSI2 signals are available for P19 which is convenient for users to debug other camera modules Note 1 if users want to use ot...

Page 42: ...dule designed by Forlinx Note data should be equal with clock differential impedance 100 3 4 13 LVDS There are two 8 lane LVDS ports on carrier board by headers with pitch of 2 0mm it can fit Forlinx...

Page 43: ...th audio WM8960 for SAI3 on carrier board can support two speaker output supports dual track earphone output and one MIC input It s designed as a 3 5mm jack on P32 with CTIA standard if inserted with...

Page 44: ...ult one we use is Quectel EC20 and M 2 Key B standard 5G wireless module the one we use is Quectel RM500Q 4G and 5G share one DCDC power and one SIM card slot and also one USB2 0 channel mount a modul...

Page 45: ...W CM358SM on carrier board WLAN IEEE 802 11 a b g n ac dual band WiFi up to 433 3Mbps BT5 0 up to 3Mbps Please use a 2 4 5Ghz duan band antenna to enhance signal Note 1 The module IO should be equippe...

Page 46: ...er board complies with PCI Express Gen3 PCIE_REF_CLK_P N of SoM can only support input clock it needs carrier board clock chip U42 with RC and EP with same source dual direction Note PCIe TX RX data a...

Page 47: ...onnectors with power anti short circuit protection 1A limited over current protection controlled by USB HUB if users don t use a HUB chip please design short circuit protection circuit to carrier boar...

Page 48: ...48 48 3 4 20 USB3 0 Type C...

Page 49: ...d USB Switch Users can take Forlinx designing for reference If users need USB2 0 OTG the port can be simplified as below Note 1 Only the SoM native USB1 can support USB OS image flashing 2 USB data li...

Page 50: ...20 are available on OKMX8MPQ C carrier board and 10 100 1000Mbps auto adaptive the upper one can support TSN SoM RGMII is mounted with PHY chip YT8521S and the dual layer RJ45 connector has internal n...

Page 51: ...nstable voltage may cause YT8521S failure 4 Simulated differential line should be with 100 differential impedance interclass equal length should be 1000mil 5 The PCB should be designed with 4 layers a...

Page 52: ...O and available for users definition 3 4 23 RTC The carrier board mounted with RTC by IIC3 and be compatible with cell battery by VCC_3V3 from D5 when carrier board power is cut off the battery can su...

Page 53: ...e less than 6 inches 4 AD28_SD2_RESET_B LD44 pin AD28_SD2_RESET_B is internal circuited to VSD_3V3 on SoM used for reset carrier board SD card please suspend it on carrier board 5 R26_NAND_DQS RU75 pi...

Page 54: ...54 54 Appendix 2 Connector connector model on SoM is AXK6F80337YG...

Page 55: ...55 55 The connector matched on carrier board is AXK5F80537YG...

Page 56: ...PQ C OKMX8MPQ C mounted with PCIe hard disk 5G 10 1 LVDS display with video playing 12 1 07 0 89 FETMX8MPQ C Powered with empty loaded 5 0 72 0 42 CPU 100 loaded 5 0 57 Sleeping mode 5 0 105 Note 1 Pe...

Page 57: ...ake sure the SoM can work except for VSYS_5V it also needs SyS_nRST BOOT configuring circuit OTG or SD card which will be convenient for users for firmware installation and system boot UART2 and UART4...

Page 58: ...58 58...

Page 59: ...59 59...

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