Forlinx SBC OKMX8MPQ-C, User Manual

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2.5.2 SoM FETMX8MPQ-C Pin Details
Table 1 LEFT_UP (P1 ) connector pins (odd)
Num Ball Signal GPIO Vol Spec. Default
LU_1 — GND — — GND GND
LU_3 AH4 UART2_TXD GPIO5_IO25 3.3V UART2(A53 debug) data sending UART2_TXD
LU_5 AF6 UART2_RXD GPIO5_IO24 3.3V UART2(A53 debug) data receiving UART2_RXD
LU_7 AE6 UART3_RXD GPIO5_IO26 3.3V UART3 data receiving UART1_CTS
LU_9 AJ4 UART3_TXD GPIO5_IO27 3.3V UART3 data sending UART1_RTS
LU_11 AF8 I2C4_SCL GPIO5_IO20 3.3V I2C4 clock I2C4_SCL
LU_13 AD8 I2C4_SDA GPIO5_IO21 3.3V I2C4 data I2C4_SDA
LU_15 — GND — — GND GND
LU_17 AH6 I2C2_SCL GPIO5_IO16 3.3V I2C2 clock I2C2_SCL
LU_19 AE8 I2C2_SDA GPIO5_IO17 3.3V I2C2 data I2C2_SDA
LU_21 AJ6 I2C3_SDA GPIO5_IO19 3.3V I2C3 data I2C3_SDA
LU_23 AJ7 I2C3_SCL GPIO5_IO18 3.3V I2C3 clock I2C3_SCL
LU_25 — GND — — GND GND
LU_27 AH8 SAI1_RXC GPIO4_IO1 1.8V SAI1 receive bit clock 4G_RST
LU_29 AF10 SAI1_RXD1 GPIO4_IO3 1.8V SAI1 receive data 1 5GPWR_RESE
LU_31 AC10 SAI1_RXD0 GPIO4_IO2 1.8V SAI1 receive data 0 5GPWR_ON/O
LU_33 AJ9 SAI1_RXFS GPIO4_IO0 1.8V SAI1 receive frame sync 4G/5G_PWR
LU_35 — GND — — GND GND
LU_37 AH9 SAI1_RXD2 GPIO4_IO4 1.8V SAI1 receive data 2 ENET1_MDC