Force Computers SPARC CPU-54, Reference Manual

Page: 33 / 138

Features Introduction
1 - 4 SPARC/CPU-54
CPU
The UltraSPARC-IIe CPU with 500 MHz has sensors for observing the
CPU on-die temperature and provides the following features:
• Four-way superscalar processor
• SPARC V9 Architecture with the VIS instruction set
• 64-bit data path and 44-bit address pointers
• 16 KByte instruction cache
• 16 KByte non-blocking primary data cache
• 256 KByte L2-Cache memory
Memory
Memory features include:
• 128 to 512 MByte on-board SDRAM
• 128 to 1536 MByte SDRAM memory module
• 1 MByte boot PROM
• Internal memory controller support of up to 2 GB SDRAM
• Supports up to 4 MByte user flash
OpenBoot
OpenBoot serves as a boot device and provides the setup for the VME-
bus interface. For further details, refer to the “OpenBoot Firmware” sec-
tion on page 4-1.