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OpenBoot Firmware

Summary of Contents for SPARC CPU-54

Page 1: ...lized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stock R...

Page 2: ...SPARC CPU 54 Reference Guide P N 220991 Revision AA May 2003...

Page 3: ...Electronics Engineers Inc PICMG CompactPCI and the CompactPCI logo are registered trademarks and the PICMG logo is a trademark of the PCI Indus trial Computer Manufacturer s Group MS DOS Windows95 Win...

Page 4: ...he Americas Europe Asia Force Computers Inc 4211 Starboard Drive Fremont CA 94538 U S A Tel 1 510 445 6000 Fax 1 510 445 5301 Email support fci com Force Computers GmbH Lilienthalstr 15 D 85579 Neubib...

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Page 6: ...his Guide Other Sources of Information Safety Notes Sicherheitshinweise 1 Introduction Features 1 3 CPU 1 4 Memory 1 4 OpenBoot 1 4 Block Diagram 1 5 CPU Board Variants 1 6 SPARC CPU 54 1 6 SPARC CPU...

Page 7: ...essories 2 8 Memory Modules 2 8 IO 54 2 8 SPARC IOBP 54 2 9 Solaris Driver Package 2 9 Setting the SCSI Termination 2 10 SCSI 1 Termination 2 10 SCSI 2 Termination 2 10 Switch Settings 2 12 Board Inst...

Page 8: ...Mouse 3 8 SCSI 3 9 On Board Connectors of the SPARC CPU 54 3 10 4 OpenBoot Firmware Introduction 4 3 CORE 4 3 CORE Workflow 4 5 CORE Commands 4 6 POST 4 6 OpenBoot 4 6 Optional Boot Parameters 4 7 Boo...

Page 9: ...Control Register 5 7 Control Register 5 8 Control and Status Register 5 9 Watchdog Timer and Temperature Control Register 5 10 Watchdog Timer and Temperature Control Status Register 5 10 Watchdog Time...

Page 10: ...rol Register 5 19 Timer Initial Control Register L 5 20 Timer Initial Control Register U 5 20 Timer Counter Status Register L 5 20 Timer Counter Status Register U 5 20 RS 422 Control and Status Regist...

Page 11: ...x SPARC CPU 54...

Page 12: ...s 2 4 Table 7 Maximum Power Consumption 2 6 Table 8 Maximum Power Consumption with SPARC MEM 54 Installed 2 6 Table 9 Switch Settings 2 13 Table 10 Customizing Solaris 8 2 20 Table 11 Required Solaris...

Page 13: ...er 5 9 Table 33 Watchdog Timer and Temperature Control Status Register 5 10 Table 34 Watchdog Timer Trigger Register 5 11 Table 35 SYSFAIL and ACFAIL Interrupt Control Register 5 12 Table 36 Reset Sta...

Page 14: ...Controls Indicators and Connectors Figure 8 SPARC CPU 54 Front Panel 3 3 Figure 9 Front Panel LEDs 3 4 Figure 10 Twisted Pair Ethernet Connector Pinout 3 6 Figure 11 Serial A B Connector Pinout RS 23...

Page 15: ...xiv SPARC CPU 54 OpenBoot Firmware Figure 18 System Overview 4 4 Figure 19 OBDIAG Main Menu 4 11 Figure 20 48 bit 6 byte Ethernet Address 4 19 Figure 21 32 bit 4 byte Host ID 4 19...

Page 16: ...00002 Same for binary numbers digits are 0 and 1 x Generic use of a letter n Generic use of numbers n nn Decimal point indicator is signaled Bold Character format used to emphasize a word Courier Char...

Page 17: ...rected Figure 2 Block Diagram of the CPU Board page 1 5 Corrected power consumption of SMEM board in Table 7 SPARC CPU 54 Maxi mum Power Consumption page 2 6 Added Software Requirements page 2 7 Corre...

Page 18: ...mands in CORE Commands page 4 6 Corrected screen shot in Boot Devices page 4 7 Added POST page 4 6 Added the OBDIAG page 4 10 Corrected Diagnostics page 4 15 Editorial changes 212466 AC June 2001 Corr...

Page 19: ...VMEbus read errors and Solaris 8 version 4 01 to Installing Solaris page 2 19 and the Troubleshooting chap ter moved section Battery Exchange to Appendix B changed Table 15 Flash Seg mentation and Wri...

Page 20: ...SPARC CPU 54 xix 220991 AA May 2003 Corrected pinout of RS 422 interface Added information on termination when using RS 422 interfaces Order No Revision Date Description...

Page 21: ...Special Inter est Group pcisig com PCI Local Bus Specification Rev2 1 PICMG PCI Special Inter est Group picmg org pcisig com PCI Local Bus Specification Rev2 2 SUN Microsys tems sun com UltraSPARC IIE...

Page 22: ...t and must not be taken as replacement for qualified personnel EMC The board has been tested in a standard Force Computers system and found to comply with the limits for a Class A digital device in th...

Page 23: ...he SPARC CPU 54 does not boot and the OpenBoot prompt does not appear Therefore never boot the SPARC CPU 54 with an unformatted floppy disk residing in a floppy drive connected to the SPARC CPU 54 Ope...

Page 24: ...ive source System Controller If more than one system controller is active in the VMEbus system the board or other VMEbus participants can be damaged Therefore always ensure that only one CPU board is...

Page 25: ...hange of lithium batteries can result in a hazardous explosion Exchange the battery before seven years of actual battery use have elapsed Always use the same type of lithium battery as is already inst...

Page 26: ...usgebildetem oder im Bereich Elektronik oder Elektrotechnik qualifiziertem Personal durchgef hrt werden Die in diesem Handbuch enthaltenen Informationen dienen ausschlie lich dazu das Wissen von Fachp...

Page 27: ...r Ein oder Ausbau des Boards den Abschnitt Action Plan auf Seite 2 3 Dr cken Sie bei Ein oder Ausbau des Boards nicht auf die Frontblende sondern benutzen Sie die Griffe Lesen Sie vor dem Ein oder Aus...

Page 28: ...den k nnen Pr fen und ndern Sie die Schalterstellungen bevor Sie das Board installieren ndern Sie die Stellungen w hrend des Betriebs kann das Board besch digt werden Austausch Erweiterung Verwenden S...

Page 29: ...chreitet Falls Sie Fragen haben wenden Sie sich an Ihren Systemadministrator Batterie Achten Sie beim Austausch der Batterie auf folgende Hinweise Fehlerhafter Austausch von Lithium Batterien kann zu...

Page 30: ...1 Introduction...

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Page 32: ...actor It includes a PCI bus sub system with 32 bit 33 MHz On board are Hardware monitor for observing board temperature OpenBoot diagnostics Universe II PCI to VMEbus PCIO chip with interfaces to the...

Page 33: ...dress pointers 16 KByte instruction cache 16 KByte non blocking primary data cache 256 KByte L2 Cache memory Memory Memory features include 128 to 512 MByte on board SDRAM 128 to 1536 MByte SDRAM memo...

Page 34: ...ntroduction Block Diagram SPARC CPU 54 1 5 Block Diagram The block diagram shows how the devices of the SPARC CPU 54 work together and which data paths they use Figure 2 Block Diagram of the CPU Board...

Page 35: ...RC CPU 54 is available as CPU board and also in combination with the I O 54 If combined with the I O 54 the SPARC CPU 54 is called SPARC CPU 54T and allows the installation of PMC modules SPARC CPU 54...

Page 36: ...54 1 7 SPARC CPU 54T The SPARC CPU 54T consists of a single slot CPU board and a single slot I O 54 which allows to mount two PMC modules For further information on the I O board refer to the IO 54 I...

Page 37: ...68 2 1 2 3 13 14 Climatic environmental requirements The SPARC CPU 54 can only be used in an restricted temperature range see Table 6 Environmental Requirements on page 2 4 for details IEC 68 2 6 27 3...

Page 38: ...pgrades and accessories use the order numbers given below Product Nomenclature In the following table you find the key for the product name extensions Table 2 Product Nomenclature SPARC CPU 54 T mmm s...

Page 39: ...6 MBit devices 500 MHz CPU with 256 KByte Cache 4 MByte user flash 110542 T 128 500 1 4 R2 128 MByte CPU board memory 2 banks 256 MBit devices 500 MHz CPU with 256 KByte cache 4 MByte user flash and I...

Page 40: ...1 IOBP 54 3 3 row I O panel for the CPU 54 and I O 54 with 3 row P2 connector pinout 108772 IOBP 54 5 5 row I O panel for the CPU 54 and I O 54 with 5 row P2 connector pinout 108773 CPU 54 AccKit 3 IO...

Page 41: ...Ordering Information Introduction 1 12 SPARC CPU 54...

Page 42: ...2 Installation...

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Page 44: ...Installation Action Plan SPARC CPU 54 2 3 Action Plan In order to install the board the following steps are necessary and will be described in further detail in the sections of this chapter...

Page 45: ...culating around the board and not to the actual component tempera ture Caution To ensure that the operating conditions are met forced air cooling is required within the chassis environment Do not oper...

Page 46: ...e Computers representative for further details The installation of the SPARC CPU 54 requires 5V power supply Minimum airflow meeting the thermal requirements see Table 6 Environmental Requirements on...

Page 47: ...e 12V supply if the 5V supply has not been loaded before Use a VMEbus board in the system which loads the 5V to prevent such systems from running into a power up deadlock Table 7 Maximum Power Consump...

Page 48: ...Package Version 2 11 or higher Intel 82559 Ethernet device Universe II PCI to VMEbus bridge On board Flash memory Temperature sensors LEDs seven segment display watchdog and floppy ejection For infor...

Page 49: ...le SPARC MEM 54 128 with 128 MByte additional memory SPARC MEM 54 512 with 512 MByte additional memory SPARC MEM 54 1024 with 1024 MByte additional memory SPARC MEM 54 1536 with 1536 MByte additional...

Page 50: ...54 Otherwise the board may be damaged The IOBP 54 provides automatic SCSI termination Therefore SW5 2 on the CPU board must be configured appropriately to dis able the corresponding backplane SCSI ter...

Page 51: ...the mentioned position Caution Only connect the SCSI cable at its end connectors and never at its middle connectors Otherwise data may be lost SCSI 2 Termination Caution If you use a flat ribbon T ca...

Page 52: ...ation Setting the SCSI Termination SPARC CPU 54 2 11 The figure below shows the SCSI bus termination concept on the SPARC CPU 54 and the IOBP 54 Figure 5 SCSI Termination Concept of SPARC CPU 54 and I...

Page 53: ...hanged before the board installation Do not set reset the switches during operation Other wise the board is damaged The SPARC CPU 54 provides five configuration switches SW4 SW5 SW6 SW7 and SW800 Swit...

Page 54: ...es on Board s Bottom Side Table 9 Switch Settings Switch No Description SW4 1 Abort key control OFF default ABORT key enabled ON ABORT key disabled 2 Reset key on front panel control OFF default RESET...

Page 55: ...4 Manual SCSI termination for SCSI 2 on P2 OFF default Termination enabled ON Termination disabled SW6 1 Reserved must be OFF 2 Boot device selection OFF default Boot from OTP PROM ON Boot from flash...

Page 56: ...2 Manual VMEbus slot 1 selection only relevant if SW800 1 is ON OFF default VMEbus slot 1 function enabled ON VMEbus slot 1 function disabled 3 External VMEbus SYSRESET OFF default VMEbus SYSRESET gen...

Page 57: ...automatically transfer the signals to the next board in the chain If the board is not plugged into an active backplane jumpers on the backplane will transmit the signals The jumpers have to be set ma...

Page 58: ...3 Switch off power Caution Before installing the board check switch settings for consistency see Table 9 Switch Settings on page 2 13 4 Plug board into system slot on left hand side Note Make sure all...

Page 59: ...front panel serial I O interface A For information on the serial interface connector pinout see the On Board Connectors of the SPARC CPU 54 section on page 3 10 2 Switch on system The monitor will dis...

Page 60: ...tem unexpectedly To avoid this problem install Solaris 8 kernel patch 108528 12 or higher For information on how to install it refer to the README file contained in the zip file The following devices...

Page 61: ...ocess the following warning may appear WARNING i2c_client_register_failed If this should be the case the warning can be ignored as it has no impact on the boot pro cess Table 10 Customizing Solaris 8...

Page 62: ...ice is shown with the driver name and instance num ber during the Solaris boot up The other way to obtain the instance number of the Ethernet devices is to look into the file etc path_to_inst In order...

Page 63: ...the FRCvme package provides a common programming interface for application and driver development to the FRCvme pack age and a detailed description of the software interface and sample pro grams For m...

Page 64: ...en segment display Accesses the temperature sensor devices To enable the temperature sensors set the OpenBoot environment variable env monitor before booting To do so enter at the prompt setenv env mo...

Page 65: ...Board Installation Installation 2 24 SPARC CPU 54...

Page 66: ...3 Controls Indicators and Connectors...

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Page 68: ...4 SPARC CPU 54 3 3 Front Panel of the SPARC CPU 54 The following figure shows the connectors keys and LEDs available on the front panel of the SPARC CPU 54 For the front panel features of the IO 54 se...

Page 69: ...is active starts flashing at hung sig nal of SPARC CPU 54 BM VMEbus busmaster and SYSFAIL LED Green If CPU board accesses VMEbus bus as master Red If SYSFAIL is asserted from Universerve II to VMEbus...

Page 70: ...y difference that the corresponding status bit B_POR in the UltraSPARC IIe Reset_Control Register is set and the DRAM refresh is not influenced Abort When enabled and toggled it instantaneously affect...

Page 71: ...faces are available at the front panel via the 10BaseT 100BaseTx Twisted Pair Ethernet TPE connectors Figure 10 Twisted Pair Ethernet Connector Pinout The Ethernet 1 interface is also accessible at th...

Page 72: ...are also provided via the respective VMEbus P2 connector Both I O interfaces can be configured as RS 232 and RS 422 The selec tion is made via the switches SW7 1 and SW7 2 Note When configuring the s...

Page 73: ...front panel via an 8 pin mini DIN connector The pinout can be seen in the following figure Figure 13 Keyboard Mouse Connector Pinout SUN Type Function If using an adapter a PS 2 type interface is also...

Page 74: ...SPARC CPU 54 3 9 SCSI The following connector pinout shows the signals of the ultra wide SCSI connector Note The board is not compliant to EN 55022 if you connect a SCSI device to the SCSI connector o...

Page 75: ...s backplane connector P1 VG 96 pin connector male VMEbus backplane connector P2 VG 160 pin connector male in case of three row factory option VG 96 pin connector male IO 54 connector P6 100 pin MBus c...

Page 76: ...BD and mouse MSE Ethernet 1 TP1R Ethernet 2 TP2R Parallel LPT SCSI SCSI Serial interface A SerA and serial interface B SerB The standard CPU board is delivered with a five row P2 VMEbus con nector How...

Page 77: ...On Board Connectors of the SPARC CPU 54 Controls Indicators and Connectors 3 12 SPARC CPU 54 Figure 17 P2 VMEbus Connector Pinout Continued Rows C D...

Page 78: ...4 OpenBoot Firmware...

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Page 80: ...n output shown in the examples can differ from the appearance of the output on your monitor according to your device tree CPU architecture For more information on the OpenBoot firmware see the OpenBoo...

Page 81: ...sh floppy and net early on the cold boot sequence of a firmware client Basic system tests that can replace existing POST in min mode System testing may be done using the POST drop in in max mode Error...

Page 82: ...OpenBoot Firmware Introduction SPARC CPU 54 4 5 CORE Workflow The following figure describes the workflow of CORE...

Page 83: ...ag switch is true for each test a message is displayed on a terminal connected to the serial I O interface A If the system does not work correctly error messages will be displayed which indicate the p...

Page 84: ...ription device speci fier Name full path or alias of the boot device Typical values are cdrom disk floppy net or tape filename Name of program to be booted The filename parameter is relative to the ro...

Page 85: ...c Disk SCSI target ID c diskb Disk SCSI target ID b diska Disk SCSI target ID a disk9 Disk SCSI target ID 9 disk8 Disk SCSI target ID 8 disk7 Disk SCSI target ID 7 disk6 Disk SCSI target ID 6 disk5 Di...

Page 86: ...k2b Disk SCSI target ID b disk2a Disk SCSI target ID a disk29 Disk SCSI target ID 9 disk28 Disk SCSI target ID 8 disk27 Disk SCSI target ID 7 disk26 Disk SCSI target ID 6 disk25 Disk SCSI target ID 5...

Page 87: ...ence of devices on all expansion buses and evaluates their characteristics such as device ID de vice type vendor ID and revision ID In order to test the hardware OBDIAG requires selftest methods for t...

Page 88: ...ring the following command at the ok prompt obdiag After entering the command obdiag at the ok prompt the OBDIAG main menu mask appears The following figure shows the main menu mask if the SPARC CPU 5...

Page 89: ...rrence of the first error or continue to test the hardware It is also possible to run the test more than once or produce a detailed print out of the test Table 23 OBDIAG Commands Command Description e...

Page 90: ...SUBTEST e2 class test SUBTEST status reg walk1 SUBTEST line size walk1 SUBTEST latency walk1 SUBTEST line walk1 SUBTEST pin test SUBTEST dma reg test SUBTEST dma func test Selftest at pci 1f 0 ebus 1...

Page 91: ...hen booting an operating system or another stand alone program and neither a boot device nor a filename is supplied the boot command of the Forth monitor takes the omitted values from the NVRAM config...

Page 92: ...e primary SCSI bus probe scsi all device path Performs probe SCSI on all SCSI buses installed in the system below the specified device tree node If device path is omitted the root node is used test de...

Page 93: ...i all The actual response depends on the devices on the SCSI buses Note A terminal message as answer to the command probe scsi all can take up to two minutes ok probe scsi all pci 1f 0 scsi 2 Target 6...

Page 94: ...he selftest of the device node Group of Devices To test a group of installed devices enter test all All devices below the root node of the device tree are tested The response depends on the devices ha...

Page 95: ...t receives a valid packet and displays an X each time it receives a packet with an error which can be detected by the network hardware interface ok watch net Internal loopback test succeeded Transceiv...

Page 96: ...ss for the Ethernet con troller the contents of the ID PROM and the version number of the OpenBoot firmware Ethernet Address and Host ID In order to see the Ethernet address and host ID enter the foll...

Page 97: ...ess The following table lists these commands Table 26 Commands to Display System Information Command Description banner Displays system banner enet addr Displays the Ethernet address idprom Displays I...

Page 98: ...ware reset For this type of reset use the command reset at the Forth command line Button power on reset In both cases the system begins with the initialization procedures If the system is reset via a...

Page 99: ...before and after execution of the Forth word before after and a short description The online help of the Forth monitor is located in the boot PROM This means that an online help is not available for a...

Page 100: ...r the virtual address x addr display the 64 bit number from location addr l addr display the 32 bit number from location addr w addr display the 16 bit number from location addr c addr display the 8 b...

Page 101: ...Activating OpenBoot Help OpenBoot Firmware 4 24 SPARC CPU 54...

Page 102: ...5 Maps and Registers...

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Page 104: ...27 PCI Addresses Considered by the PCI to EBus2 Controller PCI Address Description EBUS CS F000000016 F0FFFFFF16 Up to 16 MByte of boot and user flash 0 F100000016 F10FFFFF16 TOD NVRAM M48T58 1 F11000...

Page 105: ...hdog Timer and Temperature Control Interrupt Control and Status register 60 000716 F016 8 Watchdog Timer Trigger register 60 000816 F016 8 Reserved 60 000916 F016 8 Reserved 60 000A16 F016 8 SYSFAIL A...

Page 106: ...L 60 002716 XF16 8 Timer Counter Status register U 60 002816 FX16 8 RTB Status register 60 002916 F016 8 Reserved 60 002A16 F016 8 RS 422 Control and Status register 60 002B16 F016 8 Ethernet Configur...

Page 107: ...scription Access 1 0 COLOR Turns user LED on or off and controls color of LED 002 User LED turned off 012 User LED turned on and shines green 102 User LED turned on and shines red 112 User LED turned...

Page 108: ...off and controls color of LED 002 User LED turned off 012 User LED turned on and shines green 102 User LED turned on and shines red 112 User LED turned on and shines yellow r w 3 2 BLINK_FREQ Control...

Page 109: ...6 Bit Signal Description Access 0 Reserved Reserved r 1 Reserved Reserved r 2 EJECT_FD Ejects floppy disk in floppy disk drive 0 default Bit is cleared 1 Bit is set floppy disk ejected r w 3 RESET_STA...

Page 110: ...across the I2 C Bus Table 32 Control and Status Register Address F160000516 Bit Signal Description Access 0 SW_PLCC_ TSOP Simulates SW6 2 by software 0 Bit is cleared after reset 1 Bit is set by Softw...

Page 111: ...ontrol Status Register Address F160000616 Bit Signal Description Access 0 IE_WDT Enables Watchdog Timer Interrupt 0 Watchdog Timer interrupt is disabled 1 Watchdog Timer interrupt is enabled r w 1 IS_...

Page 112: ...Register Table 34 Watchdog Timer Trigger Register Address F160000716 Bit Signal Description Access 0 2 Reserved Reserved r 3 WDI Triggers Watchdog Timer 0 Default 1 To start Watchdog timer must be ena...

Page 113: ...Enables SYSFAIL interrupt 0 SYSFAIL interrupt enabled 1 SYSFAIL interrupt disabled r w 1 IP_SYSF Reflects if SYSFAIL interrupt is pending 0 No SYSFAIL interrupt is pending 1 SYSFAIL interrupt is pendi...

Page 114: ...n reset occurs when the power supply unit is turned on or the power supply sensor detects that one of the available power supply voltages falls below a tolerable limit Table 36 Reset Status Register A...

Page 115: ...ntrol Register Address F160001016 Bit Signal Description Access 0 SEG_A Turns seven segment LED display s segment A on or off 0 Segment turned off 1 Segment turned on w 1 SEG_B Turns seven segment LED...

Page 116: ...turned off 1 Segment turned on w 6 SEG_G Turns seven segment LED display s segment G on or off 0 Segment turned off 1 Segment turned on w 7 SEG_DP Turns seven segment LED display s segment DP on or o...

Page 117: ...ects state of switch SW7 1 0 RS 422 enabled factory option 1 default RS 232 enabled r 1 SW7_2 Reflects state of switch SW7 2 0 RS 422 enabled factory option 1 default RS 232 enabled r 2 SW7_3 Reflects...

Page 118: ...able 42 Switch 4 and 5 Status Register Address F160001216 Bit Signal Description Access 0 SW_4_4 Reflects state of switch SW4 4 which is reserved 0 Switch SW4 4 is set to ON 1 default Switch SW4 4 is...

Page 119: ...bus SYSRESET output enable switch SW800 4 0 VMEbus SYSRESET output disabled 1 default VMEbus SYSRESET output enabled r 5 VSYS_RESIN Reflects state of VMEbus SYSRESET input enable switch SW800 3 0 VMEb...

Page 120: ...he count down timer The timer counts down from its initial value to zero in steps of 10us The initial value can be set by software from 1 to 65535 which results in a timer period of 10us to 655 35 ms...

Page 121: ...able 46 Timer Initial Control Register U Address F160002516 Bit Signal Description Access 7 0 TINITU Set upper byte of timer initial value TINITU_TINITL 000116 timer period of 10 s TINITU_TINITL FFFF1...

Page 122: ...it Signal Description Access 0 REG_TTYA Selects protocol of serial transceiver for TTYA 0 RS 232 enabled 1 RS 422 enabled factory option r w 1 REG_TTYB Selects protocol of serial transceiver for TTYB...

Page 123: ...panel or the backplane The table below shows the selection for autodetect or fixed routing Table 50 Ethernet Control and Status Register Address F160002B16 Bit Signal Description Access 0 ETH_CTRL0 S...

Page 124: ...A Troubleshooting...

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Page 126: ...application software so that I O ranges match I O cards and host Board does not boot Boot device not partitioned according to used operating system Check partition according to the operat ing system...

Page 127: ...connected to power supply Connect device to power supply Wrong board configuration faulty switch setting Configure the board correctly for the respective device Devices collide with each other Devices...

Page 128: ...board Install IOBP defined for the used periph eral or system board System shuts down unexpect edly Solaris 8 version 4 01 and later performs a regular and automatic shutdown if a VME read error e g...

Page 129: ...Troubleshooting A 6 SPARC CPU 54...

Page 130: ...B Battery Exchange...

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Page 132: ...se the battery as power backup Therefore back up affected data before exchanging the battery Always use the same type of lithium battery as is already installed In order to exchange the battery follow...

Page 133: ...Battery Exchange B 4 SPARC CPU 54...

Page 134: ...ag file 4 14 diag level 4 6 diag switch 4 6 4 14 E Ethernet 3 6 except 4 12 exit 4 12 H help 4 12 4 22 L Location of switches 2 12 2 13 M Maximum power consumption 2 6 O OpenBoot 1 4 P PCIO 1 3 printe...

Page 135: ...I 2 SPARC CPU 54 what 4 12...

Page 136: ...erial No Date Of Purchase Originator Company Point Of Contact Tel Ext Address Present Date Affected Product Hardware Software Systems Affected Documentation Hardware Software Systems Error Description...

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