3131
A-S
FN-LINK TECHNOLOGY LIMITED
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Information
8. Host Interface Timing Diagram
8.1 SDIO Pin Description
The module supports SDR12(25MHz) and SDR25(50MHz, dual rates) in addition to the
1.8V default speed(25MHz) and high speed (50 MHz). It has the ability to stop the SDIO
clock and map the interrupt signal into a GPIO pin. This ‘out-of-band’ interrupt signal notifies
the host when the WLAN device wants to turn on the SDIO interface. The ability to force the
control of the gated clocks from within the WLAN chip is also provided.
SDIO Pin Description
SD 4-Bit Mode
DATA0 Data Line 0
DATA1 Data Line 1 or Interrupt
DATA2 Data Line 2 or Read Wait
DATA3 Data Line 3
CLK
Clock
CMD
Command Line
8.2 SDIO Default Mode Timing Diagram
