4—Tau 640 Digital Data Channel
Tau 640 User’s Manual
4-4
June 2011
TAU-0640-00-10, version 110
4.3 XP Bus Setting—CMOS Digital Interface
The CMOS interface is a parallel output that allows the user to access 8-bit AGC corrected data
or 14-bit data. The signal levels are 0 - 3.3 V CMOS logic and are intended to drive XP-boards
mounted directly to the Tau 640 camera. CMOS is not intended to drive a cable. An XP-board
reference design is available upon request.
Table 4-3 shows the connector pin definitions with CMOS enabled.
Note
The optional discrete input pins should be unloaded when using the CMOS output.
Table 4-3: 50-pin Hirose connector interface with CMOS output enabled
Pin #
Signal Name
Pin #
Signal Name
1
RS232_TX
2
RS232_RX
3
CMOS_LINE_VALID
4
CMOS_FRAME_VALID
5
DGND
6
DGND
7
unused
8
unused
9
LVDS_CLK_P
10
LVDS_CLK_N
11
LVDS_SYNC_P
12
LVDS_SYNC_N
13
LVDS_DATA_P1
14
LVDS_DATA_N1
15
LVDS_DATA_P2
16
LVDS_DATA_N2
17
DGND
18
DGND
19
DISCRETE0
20
CMOS_DATA13
21
EXTERNAL_SYNC
22
CMOS_DATA12
23
CMOS_DATA11
24
CMOS_DATA 10
25
CMOS_DATA9
26
CMOS_DATA8
27
DGND
28
DGND
29
CMOS_DATA7
30
CMOS_DATA6
31
CMOS_DATA5
32
CMOS_DATA4
33
CMOS_DATA3
34
CMOS_DATA2
35
CMOS_DATA1
36
CMOS_DATA0
37
DGND
38
DGND
39
CMOS_CLK
40
unused
41
DGND
42
DGND
43
VID_OUT_H
44
VID_OUT_L
45
DGND
46
3V3
47, 49
MAIN_PWR_RTN
48, 50
MAIN_PWR
