background image

 

 

Rev AN-2153 REV B 
  

©2016 Finisar Corporation AN-2153 REV B 

Page 1 of 6 

20-May-2016 
 

Application Note AN-2153 

100G QSFP28 LR4 and CWDM4 initialization Application Note Rev B 

 
Introduction 
 

The purpose of this application note is to document the recommended power-on initialization sequence of 
Finisar’s 100 Gigabit Ethernet QSFP28 LR4 and CWDM4 modules. At the time of writing this application 
note, the affected part numbers are FTLC1151xDPL (25/28G) 10km LR4 and FTLC1152xGPL (25/28G) 
2km CWDM4. 
 

The CAUI-4 (4 X 25/28G) high speed signal that propagates from the host ASIC to the 

module’s transmit 

electrical input can be affected by ISI (inter symbol interference) when the electrical signal is transmitted 
over long host trace lengths. The accumulation of ISI can distort the high speed signals, sufficient to 
cause eye closure at the TP1a CAUI-4 input to the QSFP28 module.  

Finisar’s QSFP28 modules implement a transmit input equalizer function that is designed to compensate 
the ISI and jitter, to provide an open eye to the transmit CDR (clock and data recovery). Equalization is a 
signal processing technique that boosts the high frequency component of the signal and reduces ISI. This 
function is called CTLE (Continuous Time Linear Equalization) and is implemented at the CDR on all 4 
input lanes.  

Finisar

’s QSFP28 modules have fixed programmable CTLE implementation.  

For more details on the CTLE function please refer to the Appendix on page 5 of this application note. 

 

How to use this Application Note 
 

This application note outlines the default CTLE configuration type in QSFP 28 LR4 and CWDM4 modules 
and explains how each CTLE method defines the power on sequencing of the module. This will allow the 
host to determine which CTLE setting best suits their application.  
 
 

Applicable Documents, 

Standards and MSA’s 

 

a.  SFF-8636, QSFP28 100G Common Management  Interface Rev 2.6, June 19

th

 2015. 

b.  SFF-8679, QSFP28 QSFP28 4X Base Electrical Specification Rev 1.7 August 12

th

 2014 

c.  SFF-8024, SFF Committee Cross Reference, Rev 3.5, December 2

nd

  2015 

d.  IEEE802.3bm D3p3

 

e.  OIF-CEI-03.1 Common Electrical I/O (CEI) Electrical  and Jitter Interoperability agreements for 

6G+ bps, 11G+ bps and 25G+ bps I/O

 

f.  OIF-CEI-28G-VSR Common Electrical Interface - 28G-VSR (CEI-28G-VSR) 

 
 
 

Summary of Contents for QSFP28 LR4

Page 1: ...ansmit CDR clock and data recovery Equalization is a signal processing technique that boosts the high frequency component of the signal and reduces ISI This function is called CTLE Continuous Time Linear Equalization and is implemented at the CDR on all 4 input lanes Finisar s QSFP28 modules have fixed programmable CTLE implementation For more details on the CTLE function please refer to the Appen...

Page 2: ... support for auto adaptive equalizer set to 0 for unsupported SFF 8636 Table 6 22 Page 0h register 193 bit 2 indicates Manual i e fixed programmable equalizer support set to 1 for supported The magnitude of the transmitter input equalization supported by the transceiver is identified in Page 03h Byte 224 Here the maximum gain supported is 10dB for fixed programmable mode The SFF 8636 Table 6 34 de...

Page 3: ...ny non default register value will need to be written upon each module power cycle or reset Initialization Process in fixed programmable CTLE mode In manual CTLE mode we recommend that the host follow the initialization sequence described below 1 Host board is powered on and initialized The QSFP28 module may or may not already be plugged into the host board Host should implement low power mode LPM...

Page 4: ...isable the module goes to high power state Both QSFP28 LR4 and CWDM4 are configured as cooled devices so the module ready time including TEC stabilization time is a maximum of 5 seconds 9 Once the optical connections are implemented the host physical layer link indicator should be asserted 10 Host will need to read Page 0 byte 2 to clear the latched interrupt state Interrupt pin 28 will go to high...

Page 5: ...ace The equalizer gain function is given by the following function 𝐻 𝑓 𝐺𝑃1𝑃2 𝑍1 𝑗2𝜋𝑓 𝑍1 𝑗2𝜋𝑓 𝑃1 𝑗2𝜋𝑓 𝑃2 Where 𝐻 𝑓 is the CTLE transfer function G is the CTLE gain 𝑃1 𝑃2 are the CTLE poles in Grad s 𝑍1 is the CTLE zero in Grad s 𝑗 is the square root of 1 𝑓 is the frequency in GHz The graph below represents this function CTLE gain refers to the relative amount of gain peaking at 12 89 GHz compared t...

Page 6: ... REV B 2016 Finisar Corporation AN 2153 REV B Page 6 of 6 20 May 2016 Finisar Contact Information Finisar Corporation 1389 Moffett Park Drive Sunnyvale CA 94089 1134 408 548 1000 www finisar com sales finisar com ...

Reviews: