Rev AN-2153 REV B
©2016 Finisar Corporation AN-2153 REV B
Page 4 of 6
20-May-2016
7.
The module ID EEPROM is read and the host configures to the appropriate settings. Host can
re-configure the CTLE setting if required.
8.
The host releases LPMode pin and releases Tx Disable, the module goes to high power state.
Both QSFP28 LR4 and CWDM4 are configured as cooled devices, so the module ready time
including TEC stabilization time is a maximum of 5 seconds.
9.
Once the optical connections are implemented, the host physical layer link indicator should be
asserted.
10.
Host will need to read Page 0 byte 2 to clear the latched interrupt state. Interrupt pin 28 will go
to high logic state.
11.
The MAC/PCS interface can start transmitting data.
