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Table 3-7 Definition of pins of USB 3.0 interfaces

Pin Name

Pin No.

I/O

Description

Remarks

USB_SS_RX1_P

269

USB 3.1 differential data

USB_SS_RX1_M

254

USB 3.1 differential data

reception-

USB_SS_TX1_P

270

USB 3.1 differential data -

USB_SS_TX1_M

255

USB 3.1 differential data sending-

USB 3.1 differential data

USB_SS_RX0_P

173

USB_SS_RX0_M

175

USB 3.1 differential data

reception-

USB_SS_TX0_P

172

USB 3.1 differential data -

USB_SS_TX0_M

174

USB 3.1 differential data sending-

DP_AUX_N

263

I/O

DisplayPort auxiliary transmission

channel-

DP_AUX_P

274

I/O

DisplayPort auxiliary transmission

USB_PHY_PS

276

USB front and back plug logo

The reference design of USB 2.0 interface circuit is shown in the following figure:

Summary of Contents for SC138-NA Series

Page 1: ...on forbidden without Fibocom Wireless Inc written authorization All rights reserved FIBOCOM SC138 EAU Series Hardware Guide 1 88 FIBOCOM LTE Module SC138 NA Series Hardware Guide Version V1 0 1 Date 2...

Page 2: ...Reproduction forbidden without Fibocom Wireless Inc written authorization All rights reserved FIBOCOM SC138 NA Series Hardware Guide 2 88 Applicability Type No Product Model Description 1 SC138 NA...

Page 3: ...dual is prohibited to excerpt copy any part of or the entire document or transmit the document in any form Note The document is subject to update from time to time owing to the product version upgrade...

Page 4: ...M SC138 NA Series Hardware Guide 4 88 Revision History Version Author Reviewer Approver Date Description V1 0 0 Tan Qiuye Tu Min Chen Guojiang 2020 12 29 Initial version V1 0 1 Ye Xincai Huang Feng Tu...

Page 5: ...2 1 Product Introduction 11 2 2 Performance 11 2 3 Pin Definition 19 2 3 1 Pin Distribution 19 2 3 2 Pin Description 19 3 Application Interface 35 3 1 Power 35 3 1 1 Power Input 35 3 1 2 VRTC 37 3 1 3...

Page 6: ...9 Audio 62 3 19 1 Audio Interface Definition 62 3 19 2 Microphone Circuit Design 63 3 19 3 Handset Circuit Design 64 3 19 4 Earphone Interface Circuit Design 64 3 19 5 Speaker Circuit Design 65 3 20 F...

Page 7: ...7 Electrical ALT and RF Performance 79 7 1 Recommended Parameters 79 7 2 Operating Current 79 7 3 Electrostatic Protection 80 8 Structural Specification 81 8 1 Product Appearance 81 8 2 Structure Size...

Page 8: ...Equipment UE conformance specification Radio transmission and reception FDD Part 1 Conformance specification 3GPP TS 36 521 1 V12 9 0 User Equipment UE conformance specification Radio transmission an...

Page 9: ...802 11n IEEE Std 802 11a IEEE Std 802 11g IEEE Std 802 11ac IEEE 802 11 2007 WLAN MAC and PHY June 2007 Bluetooth Radio Frequency TSS and TP Specification 1 2 2 0 2 0 EDR 2 1 2 1 EDR 3 0 3 0 HS Augus...

Page 10: ...Reproduction forbidden without Fibocom Wireless Inc written authorization All rights reserved FIBOCOM SC138 NA Series Hardware Guide 10 88 1 3 Related Documents FIBOCOM SC138 Series SMT Design Guide...

Page 11: ...core system of wireless intelligent products The corresponding network type and the band of SC138 modules are shown in the following table Table 2 1 Available band of SC138 NA Mode Band WCDMA Band 2 4...

Page 12: ...A Support 16 QAM 64 QAM and QPSK modulation CAT8 HSUPA maximum uplink rate 11 4 Mbps CAT24 DC HSPA maximum downlink rate 42 Mbps LTE characteristics Support FDD TDD R12 CAT4 UL CAT5 DL CAT4 Support 1...

Page 13: ...plifier output USB interface USB 2 0 high speed HS interface with the maximum data transmission rate of 480 Mbps USB 3 1 super speed SS interface with the maximum data transmission rate of 5 Gbps Supp...

Page 14: ...formance meets the requirements of 3GPP standard 2 When the modules work in this temperature range their functions are normal but relevant performance may not meet the requirements of 3GPP standard An...

Page 15: ...wish to change the antenna trace design In this case a Class II permissive change application is required to be filed by the USI or the host manufacturer can take responsibility through the change in...

Page 16: ...module The end user manual shall include all required regulatory information warning as show in this manual Federal Communication Commission Interference Statement This device complies with Part 15 of...

Page 17: ...r is only FCC authorized for the specific rule parts i e FCC transmitter rules listed on the grant and that the host product manufacturer is responsible for compliance to any other FCC rules that appl...

Page 18: ...g interference that may cause undesired operation L metteur r cepteur exempt de licence contenu dans le pr sent appareil est conforme aux CNR d Innovation Sciences et D veloppement conomique Canada ap...

Page 19: ...c written authorization All rights reserved FIBOCOM SC138 NA Series Hardware Guide 19 88 2 3 Pin Definition 2 3 1 Pin Distribution NC stands for No Connect The pin at this position is reserved and no...

Page 20: ...The pins of SC138 modules are described in the following table Pin Name Pin No I O Pin Description Remarks Power VBAT 4 5 6 PI Main power supply input VRTC 126 PI PO RTC power supply pin VREG_CAM0_ DV...

Page 21: ...ight sensor power supply VREG_3P0 266 PO 3 0 V voltage output VREG_L15A_3P1 28 241 PO 3 1 V voltage output GN D 3 7 10 13 15 27 36 51 62 69 74 77 79 93 95 119 121 131 133 136 143 146 149 152 153 154 1...

Page 22: ...22 DI U SIM 1 plug detection Off by default UIM2_DATA 20 I O U SIM 2 data signal UIM2_CLK 19 DO U SIM 2 clock signal UIM2_RESET 18 DO U SIM 2 reset signal UIM2_DETECT 17 DI U SIM 2 plug detection Off...

Page 23: ...default SNS_I2C_SDA 88 OD I2C data line Being used for sensor by default TS_I2C_SCL 41 OD I2C clock Being used for TP by default TS_I2C_SDA 150 158 OD I2C data line Being used for TP by default CAM0_...

Page 24: ..._RX1_ P 269 DI USB 3 1 differential data reception USB_SS_RX1_ M 254 DI USB 3 1 differential data reception USB_SS_TX1_ P 270 DO USB 3 1 differential data sending USB_SS_TX1_ M 255 DO USB 3 1 differen...

Page 25: ...sending QUP1 SE0 UART_RX 46 DI UART data reception QUP1 SE0 UART_CTS TS 1_I2C_SDA 47 DI UART clear to send QUP1 SE0 Can be configured to I3C UART_RFR IS1 _I2C_CLK 48 DO UART request to send QUP1 SE0 C...

Page 26: ...Flash Memory type configure Display Screen Interface MIPI_DSI0_CL K_P 53 AO Main TP MIPI clock MIPI_DSI0_CL K_N 52 AO Main TP MIPI clock MIPI_DSI0_LA NE0_P 55 AI AO Main TP MIPI Lane0 MIPI_DSI0_LA NE0...

Page 27: ...P interface TS0_INT_N 42 DI Main TP interrupt signal TS0_RST_N 43 DO Main TP reset signal Camera Interface MIPI_CSI2_CL K_P 64 AO Camera 2 MIPI clock MIPI_CSI2_CL K_N 63 AO Camera 2 MIPI clock MIPI_CS...

Page 28: ...amera 3 MIPI clock MIPI_CSI0_LA NE0_P 73 AI AO Camera 3 MIPI Lane 0 MIPI_CSI0_LA NE0_N 72 AI AO Camera 3 MIPI Lane 0 MIPI_CSI0_LA NE1_P 184 AI AO Camera 3 MIPI Lane 1 MIPI_CSI0_LA NE1_N 185 AI AO Came...

Page 29: ...1 MIPI Lane 1 MIPI_CSI1_LA NE1_N 259 AI AO Camera 1 MIPI Lane 1 MIPI_CSI1_LA NE2_P 273 AI AO Camera 1 MIPI Lane 2 MIPI_CSI1_LA NE2_N 260 AI AO Camera 1 MIPI Lane 2 MIPI_CSI1_LA NE3_P 262 AI AO Camera...

Page 30: ...AI Earphone MIC input MIC2_IN_N 141 AI Earphone MIC input MIC1_N 144 AI Main MIC differential input MIC1_P 145 AI Main MIC differential input MIC3_IN_N 233 AI Auxiliary MIC differential input MIC3_IN...

Page 31: ...downloading The high level 1 8 V is effective and the module cannot be pulled up before starting GPIO Interface GPIO_32 96 I O General GPIO 1 8 V power domain B PD nppukp Boot Config GPIO_95 40 I O B...

Page 32: ...7 102 I O B PD nppukp GPIO_130 220 I O B PD nppukp GPIO_132 221 I O B PD nppukp GPIO_92 38 I O B PD nppukp GPIO_93 39 I O B PD nppukp GPIO_95 40 I O B PD nppukp GPIO_123 99 I O B PD nppukp GPIO_31 86...

Page 33: ...following table Pin Number GPIO QUP Configuration Function 1 Function 2 Function 3 Function 4 115 GPIO_0 QUP0 SE0 L0 UART_CTS SPI_MISO I2C_SDA 116 GPIO_1 L1 UART_RFR SPI_MOSI I2C_SCL 113 GPIO_2 L2 UAR...

Page 34: ...PI_CS2 88 GPIO_28 QUP1 SE2 L0 I2C_SDA 87 GPIO_29 L1 I2C_SCL 104 GPIO_30 QUP1 SE1 L0 UART_CTS SPI_MISO I2C_SDA 86 GPIO_31 L1 UART_RFR SPI_MOSI I2C_SCL 96 GPIO_32 L2 UART_TX SPI_SCLK 97 GPIO_33 L3 UART_...

Page 35: ...lls to below 3 V the module may power off or restart The power supply voltage drop is shown in the following figure Burst Transmit Burst Transmit 3V Drop 500mV VBAT 3 5V Figure 3 1 Voltage drop 3 1 1...

Page 36: ...estroyed The reference design of power supply circuit is shown in the following figure Figure 3 2 Reference design of power supply circuit The filter capacitor design of power supply is shown in the f...

Page 37: ...lock inside the module When the VBAT power supply of the module is powered on VRTC will output voltage otherwise it is powered by external power supply for example button battery if the real time cloc...

Page 38: ...ault Voltage V Drive Current mA VREG_CAM0_DVDD_1P104 0 312 1 304 1 1 600 VREG_L9A_1P8 1 504 2 000 1 8 600 VREG_L12A_1P8 1 504 2 000 1 8 300 VREG_CAM_AF_2P8 1 5 3 4 2 8 400 VREG_L22A_2P96 1 504 3 544 2...

Page 39: ...estart sleep wakeup control 3 2 1 1 Startup After the VBAT is powered on the trigger module starts up through pulling down the KEY_PWR_N pin for 2s to 8s The design of key startup circuit and OC drive...

Page 40: ...will be forced to shut down The forced shutdown timing sequence is shown in the following figure Figure 3 7 Shutdown timing sequence In case of system abnormality or crash the modules can be forced t...

Page 41: ...I Interface None 3 4 USB Interface SC138 series modules support 1 channel USB 3 0 interfaces being downward compatible with USB 2 0 interfaces USB 2 0 interfaces support HS 480 Mbps mode being downwar...

Page 42: ...O USB 3 1 differential data sending USB_SS_TX1_M 255 DO USB 3 1 differential data sending USB 3 1 differential data reception USB_SS_RX0_P 173 DI USB_SS_RX0_M 175 DI USB 3 1 differential data receptio...

Page 43: ..._D M U SB _D P U SB _I D V BU S _D ET 4V G N D 10K Figure 3 8 USB 2 0 interface reference circuit design C onnect or V BU S D M D P I D G N D M odul e U SB _D M U SB _D P U SB _I D V BU S _D ET V BA T...

Page 44: ...mum transmission rate of 480 Mbps PCB Layout must observe the following requirements USB_DP and USB_DM signal lines are required to be of equal length and the length difference of the differential lin...

Page 45: ...3 8 Definition of pins of UART interfaces Pin Name Pin No I O Description Remarks DBG_UART_TX 90 DO UART data transmission Debug interface DBG_UART_RX 89 DI UART data receiving UART_TX 45 DO UART data...

Page 46: ...138 series modules provide a set of SPI interfaces and only support the main device mode The pin definition is shown in the following figure Table 3 9 Definition of pins of SPI interfaces Pin Name Pin...

Page 47: ...A_1P8 21 PO U SIM 2 power supply The reference circuit of U SIM interface is shown in the following figure Figure 3 12 U SIM reference circuit U SIM design considerations 1 The length of route from th...

Page 48: ...nterfaces Pin No Pin Name I O Description Remarks SDC2_DATA3 34 I O SD data interface SDC2_DATA2 33 I O SD data interface SDC2_DATA1 32 I O SD data interface SDC2_DATA0 31 I O SD data interface SDC2_C...

Page 49: ...GPIO SC138 series modules have abundant GPIO resources the interface level is 1 8 V and the pin definition is shown in the following table Table 3 12 GPIO list Pin Name Pin No Reset State Interrupt Fu...

Page 50: ...ith programmable options after the colon PU nppdkp pull up by default with programmable options after the colon KP nppdpu floating by default with programmable options after the colon 3 10 I2 C SC138...

Page 51: ...line When mounting multiple peripherals on the I2C channel please ensure the uniqueness of each peripheral address When mounting peripherals with high real time performance requirements do not share...

Page 52: ...oot Config Flash Memory type configure 3 13 Battery Power Supply Interface None 3 14 Motor Drive Interface None 3 15 LCM SC138 series module screen interfaces are based on MIPI_DSI standard supporting...

Page 53: ...D backlight PWM control LCD1_BL_EN 211 DO LCD backlight enabling control LCD_TE 50 DI LCD refreshing synchronization signal NC when it is not in use The reference circuit of LCM interface is shown in...

Page 54: ...the set is controlled within 0 7 mm 6 The length difference between sets is controlled within 1 4 mm 7 It is recommended that the spacing between differential lines in the group should be 1 5 times t...

Page 55: ...upport 3 4 4 4 Lane or 4 4 4 2 1 Lane cameras It is equipped with 3 cameras by default Support 21 MP pixel camera at maximum The camera interface pin definition is shown in the following table Table 3...

Page 56: ..._LANE1_P 184 AI AO Camera 3 MIPI Lane1 MIPI_CSI0_LANE1_N 185 AI AO Camera 3 MIPI Lane1 MIPI_CSI0_LANE2_P 186 AI AO Camera 4 MIPI Lane2 MIPI_CSI0_LANE2_N 187 AI AO Camera 4 MIPI Lane2 MIPI_CSI0_LANE3_P...

Page 57: ...mera 1 is shown in the following figure Module MIPI_CSI1_CLK_P CAM1_RST_N MIPI_CSI1_CLK_N MIPI_CSI1_LAN3_P MIPI_CSI1_LAN3_N MIPI_CSI1_LAN2_P MIPI_CSI1_LAN2_N MIPI_CSI1_LAN1_P MIPI_CSI1_LAN1_N MIPI_CSI...

Page 58: ..._P MIPI_CSI2_LAN0_N CAM Connector CAM2_I2C_SDA CAM2_I2C_SCL CAM2_PWD_N CAM2_CLK CLK_P MCLK CLK_N DAT3_P DAT3_N DAT2_P DAT1_P DAT1_N C A M C onnect or PWD RST SCL SDA DAT2_N DAT0_P DAT0_N V R E G _L12A...

Page 59: ...wn in the following figure Module MIPI_CSI0_CLK_P CAM0_RST_N MIPI_CSI0_CLK_N MIPI_CSI0_LAN0_P MIPI_CSI0_LAN0_N MIPI_CSI0_LAN1_P MIPI_CSI0_LAN1_N CAM Connector CAM2_I2C_SDA CAM2_I2C_SCL CAM0_PWD_N CAM0...

Page 60: ...by a differential impedance of 100 with an error of 10 4 The total length of the route does not exceed 300 mm 5 The length difference of the differential lines in the set is controlled within 0 7 mm 6...

Page 61: ...ict 3 The analog voltage AVDD route should be away from the interference source to avoid the power noise 4 It is recommended to place an LDO with high power supply rejection ratio close to the camera...

Page 62: ...ive output CDC_EAR_P 134 AO Handset output Load of 32 and power of 123 mW CDC_EAR_N 135 AO Handset output CDC_HPH_L 139 AO Earphone left channel output CDC_HPH_REF 138 Earphone reference ground CDC_HP...

Page 63: ...e earphone output as the input source of the external power amplifier For double ended input use two channels For single ended input the channel can be configured by software 3 The earphone reference...

Page 64: ...de 64 88 Figure 3 20 Microphone circuit design 3 19 3 Handset Circuit Design M odul e CDC_EAR_N CDC_EAR_P 33pF 10 0pF 33 pF Figure 3 21 Handset circuit design 3 19 4 Earphone Interface Circuit Design...

Page 65: ...ding Interface Design SC138 series modules provide FORCE_USB_BOOT pins as emergency downloading interfaces Short circuit the USB_FORCE_BOOT and VREG_L9_1P8 pins when starting up and the module can ent...

Page 66: ...between the module and the antenna connector or feedpoint for antenna commissioning Two parallel devices are directly jumped and connected to the RF route without branch The reference circuit is shown...

Page 67: ...T5 0 2402 2480 MHz 3 21 2Circuit Reference Design WIFI BT antenna connection reference circuit is shown in the following figure Figure 3 26 WIFI BT reference circuit 3 22 GNSS Antenna GNSS supports GP...

Page 68: ...LNA is built into the SC138 series module and the passive antenna is selected in the whole machine design Microstrip line is recommended for the GNSS RF routing the insertion loss is controlled withi...

Page 69: ...supply is required to be stable and clean It is recommended to use LDO with high performance to power the antenna The gain of active antenna is required to be 17 dB If the gain is 17 dB it is necessar...

Page 70: ...3 2 7GHz WIFI BT Standing wave ratio 2 Gain dBi 1 Maximum input power W 5 Input impedance 50 Polarization type vertical direction Insertion loss 1dB GNSS Frequency range 1559 MHz 1607 MHz Polarizatio...

Page 71: ...the routing width W the ground clearance S and the height of the reference ground plane H The characteristic impedance of PCB is usually controlled by microstrip line and coplanar waveguide In order...

Page 72: ...e and ALT of RF signal the following design principles are recommended in the circuit design The impedance simulation calculation tools shall be used to accurately control the 50 impedance of the RF s...

Page 73: ...ries Hardware Guide 73 88 The reference ground plane of RF signal line shall be complete adding a certain amount of ground holes around the signal line and the reference ground can help improve the RF...

Page 74: ...Wake on WLAN WoWLAN Support ad hoc mode Support WAPI Support AP mode Support Wi Fi Direct Support MCS 0 7 for HT20 and HT40 if the 2 4G WIFI 40M needs to be opened the ini file shall be configured but...

Page 75: ...0 3 802 11n MCS0 20 18 0 3 MCS7 20 15 0 3 MCS0 40 17 0 3 MCS7 40 14 0 3 802 11ac MCS0 20 17 0 3 MCS8 20 14 0 3 MCS0 40 16 0 3 MCS9 40 13 0 3 MCS0 80 15 0 3 MCS9 80 12 0 3 Table 5 2 WIFI receiving sen...

Page 76: ...0 62 0 2 The sensitivity here is typical 5 3 Bluetooth Overview SC138SC138 series modules support BT5 0 BR EDR BLE specifications and the modulation mode supports GFSK the channel bandwidth of 8 DPSK...

Page 77: ...te Rate Throughput Note BT1 2 1Mbit s 80Kbit s BT2 0 EDR 3Mbit s 80Kbit s BT3 0 HS 24Mbit s For details see 3 0 HS BT5 0 LE 24Mbit s For details see 5 0 LE 5 4 Bluetooth Performance Indicators Test co...

Page 78: ...nd other positioning systems LNA is embedded in the module which can effectively improve the sensitivity of GNSS 6 2 Performance Index Test conditions supply voltage 3 8 V ambient temperature 25 C Tab...

Page 79: ...erature 40 25 85 C 7 2 Operating Current Test conditions supply voltage 3 8 V ambient temperature 25 C Table 7 2 SC138 NA operating current Parameter Description Condition Type Unit Ioff Power Off Pow...

Page 80: ...by human body static electricity and charged friction between microelectronics it may cause damage to the module through various ways so ESD protection shall be paid attention to ESD protection measu...

Page 81: ...reserved FIBOCOM SC138 NA Series Hardware Guide 81 88 8 Structural Specification 8 1 Product Appearance 8 2 Structure Size 8 3 Reference PCB Bonding Pad Design For details of recommended design of PC...

Page 82: ...COM SC138 NA Series Hardware Guide 82 88 9 Production and Storage 9 1 SMT Patch For details of SMT production process parameters and related requirements see FIBOCOM SC138 Series SMT Design Guide 9 2...

Page 83: ...g GMSK Gaussian Minimum Shift Keying HSDPA High Speed Down Link Packet Access IMEI International Mobile Equipment Identity Imax Maximum Load Current LED Light Emitting Diode LSB Least Significant Bit...

Page 84: ...URC Unsolicited Result Code U SIM Universal Subscriber Identity Module USSD Unstructured Supplementary Service Data Vmax Maximum Voltage Value Vnorm Normal Voltage Value Vmin Minimum Voltage Value VI...

Page 85: ...production forbidden without Fibocom Wireless Inc written authorization All rights reserved FIBOCOM SC138 NA Series Hardware Guide 85 88 Abbreviation Meaning WCDMA Wideband Code Division Multiple Acce...

Page 86: ...re Guide 86 88 Appendix B GPRS Coding Scheme Table B 1 GPRS coding scheme Coding Mode CS 1 CS 2 CS 3 CS 4 Code Rate 1 2 2 3 3 4 1 USF 3 3 3 3 Pre coded USF 3 6 6 12 Radio Block excl USF and BCS 181 26...

Page 87: ...uplink and downlink Expressed as 3 1 or 2 2 the first number represents the number of downlink slots and the second number represents the number of uplink slots Active slot represents the total number...

Page 88: ...05kbps 18 1kbps 36 2kbps CS 2 GMSK 13 4kbps 26 8kbps 53 6kbps CS 3 GMSK 15 6kbps 31 2kbps 62 4kbps CS 4 GMSK 21 4kbps 42 8kbps 85 6kbps MCS 1 GMSK C 8 80kbps 17 6kbps 35 2kbps MCS 2 GMSK B 11 2kbps 2...

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