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FIBOCOM L860-GL Series Hardware Guide
Page 35 of 60
PCIe Interface Definition
Pin#
Pin Name
I/O Reset Value Description
Type
41
PETn0
O
-
PCIe TX differential signal
Negative
-
43
PETP0
O
-
PCIe TX differential signal
Positive
-
47
PERn0
I
-
PCIe RX differential signal
Negative
-
49
PERP0
I
-
PCIe RX differential signal
Positive
-
53
REFCLKN
I
-
PCIe reference clock signal
Negative
-
55
REFCLKP
I
-
PCIe reference clock signal
Positive
-
50
PERST#
I
PU
Asserted to reset module PCIe interface
default. If module went into coredump, it will
reset whole module, not only PCIe interface.
Active low, internal pull up
(10KΩ)
3.3V
52
CLKREQ#
I/O PU
Asserted by device to request a PCIe
reference clock be available (active clock
state) in order to transmit data. It also used by
L1 PM Sub states mechanism, asserted by
either host or device to initiate an L1 exit
.
Active low, internal pull up
(10KΩ)
3.3V
54
PEWAKE#
O
L
Asserted to wake up system and reactivate
PCIe link from L2 to L0, it depends on system
whether supports wake up functionality.
Active low, open drain output and should add
external pull up (100
KΩ) on platform
3.3V
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