Fiberplex SFP-BHDVXC-0000-L, User Manual

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1. RD± Outputs are AC‐coupled inside the module
2. TD± Inputs are AC‐coupled inside the module
3. 100Ω Load condition
4. SD‐SDI signal, PRBS210‐1, Reclock input = 31psp‐p
5. HD‐SDI signal, PRBS210‐1, Reclock input = 24psp‐p
6. 3G‐SDI signal, PRBS210‐1, Reclock input = 22psp‐p
7. Measured from first SDI transition until Lock Detect (LD) is enable by Reclocker
SDI Characteristics Symbol Min Typ Max Unit
SDI RX (Input)
Input Voltage Swing V
SDI
720 800 950 mV
P‐P
Input Return Loss
(Bandwidth 0‐1.5GHz)
IRL
0‐1.5G
15 18 ‐ dB
(Bandwidth 1.5‐3GHz) IRL
1.5‐3G
10 13 ‐ dB
Jitter SD‐SDI
(0‐350m Belden 1694A)
‐ ‐ 0.2 UI
(350‐400m Belden 1694A) ‐ 0.2 ‐ UI
Jitter HD‐SDI
(0‐170m Belden 1694A)
‐ ‐ 0.25 UI
(170‐200m Belden 1694A)
‐ 0.3 ‐ UI
Jitter 3G‐SDI
(0‐110m Belden 1694A)
‐ ‐ 0.3 UI
(110‐140m Belden 1694A)
‐ 0.35 ‐ UI
Cable Length (Belden 1694A) SD‐SDI ‐ 350 400 m
HD‐SDI ‐ 170 200 m
3G‐SDI ‐ 110 140 m
SDI TX (Output)
Output Voltage Swing (75Ω Load) V
SDO
720 800 880 mV
Output Return Loss
(Bandwidth 0‐1.5GHz)
ORL
0‐1.5G
15 27 ‐ dB
(Bandwidth 1.5‐3GHz) ORL
1.5‐3G
10 13 ‐ dB
Output Jitter SD‐SDI 1 t
jit‐SD
‐ 0.014 ‐ UI
P‐P
HD‐SDI 2 t
jit‐HD
‐ 0.057 ‐ UI
P‐P
3G‐SDI 3 t
jit‐3G
‐ 0.119 ‐ UI
P‐P
Rise/Fall Time (80%‐20%)
Rate_Select = 0 (SD‐SDI)
t
r‐SD
, t
f‐SD
400 ‐ 800 ps
Rate_Select = 1 (HD/3G‐SDI)
tr
‐HD
, t
f‐HD
‐ 90 135 ps
Mismatched in Rise/Fall
Rate_Select = 0 (SD‐SDI)
‐ ‐ 50 ps
Rate_Select = 1 (HD/3G‐SDI) ‐ ‐ 30 ps
Duty Cycle Distortion
Rate_Select = 0 (SD‐SDI)
‐ 100 ‐ ps
Rate_Select = 1 (HD‐SDI) ‐ 30 ‐ ps
Rate_Select = 1 (3G‐SDI)
‐ 27 ‐ ps
Overshoot
Rate_Select = 0 (SD‐SDI)
‐ ‐ 8 %
Rate_Select = 1 (HD/3G‐SDI)
‐ ‐ 10 %
1. SD‐SDI signal, PRBS210‐1, Reclock input = 31psp‐p
2. HD‐SDI signal, PRBS210‐1, Reclock input = 24psp‐p
3. 3G‐SDI signal, PRBS210‐1, Reclock input = 22psp‐p
Timing Characteristics Symbol Min Typ Max Unit
MOD_DEF1 (Input) Clock Rate1 ‐ ‐ 400 kHz
1. If host does not support clock stretching, MOD_DEF1 (SCL) clock rate should be set to 100kHz maximum.