FabiaTech FP8100 Series, User Manual

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FabiaTech Corporation
53
CMOS RAM Map
Register Description
00h -10h
Standard AT-compatible RTC and Status and Status
Register data definitions
11h – 13h Varies
14h Equipment
Bits 7-6 Number of Floppy Drives
00 1 Drive
01 2 Drives
Bits 5-4 Monitor Type
00 Not CGA or MDA 01 40x25 CGA
01 2 Drives 80x25 CGA
Bits 3 Display Enabled
0 Disabled
1 Enabled
Bit 2 Keyboard Enabled
00 Not CGA or MDA 01 40x25 CGA
01 2 Drives 80x25 CGA
Bit 1 Math Coprocessor Installed
0 Absent
1 Present
Bit 0 Floppy Drive Installed
0 Disabled
1 Enabled
15h Base Memory (in 1KB increments), Low Byte
16h Base Memory (in 1KB increments), High Byte
17h IBM-compatible memory (in 1KB increments), Low Byte
18h IBM-compatible memory (in 1KB increments), High
Byte (max 15 MB)
19h-2Dh Varies
2Eh
Standard CMOS RAM checksum, high byte
2Fh Standard CMOS RAM checksum, low byte
30h IBM-compatible Extended Memory, Low Byte (POST) in
KB
31h IBM-compatible Extended Memory, High Byte (POST)
in KB
32h Century Byte
33h Reserved. Do not use
34h Reserved. Do not use
35h Low byte of extended memory (POST) in 64 KB
36h High byte of extended memory (POST) in 64 KB
37h-3Dh Varies
3Eh
Extended CMOS Checksum, Low Byte (including 34h-
3Dh)
3Fh Extended CMOS Checksum, High Byte (including 34h-
3Dh)