M
ODEL
SL599 V
ERSION
V_1.0
P
REPARED BY
H/W
D
ATE
2007.04.11
S
UBJECT
T
ECHNICAL
M
ANUAL
P
AGE
14/52
SL599
T
ECHNICAL
M
ANUAL
3.1
Processor Core
The Micro-Controller Unit subsystem in MT6227 uses the 32-bit Arm7EJ-S RISC processor that is based
on the Von Neumann architecture with a single 32-bit data bus carrying both instructions and data. The
memory interface of ARM7EJ-S is totally compliant to AMBA based bus system, which allows direct
connection to the AHB Bus.
3.2
Memory Management
The processor core of MT6227 supports only memory addressing method for instruction fetch and data
access. It manages a 32bit address space that has addressing capability up to 4GB. System RAM, System
ROM , Registers, MCU Peripherals and external components are all mapped onto such 32-bit address space,
as depicted in Figure 7.
Figure 7. Memory Layout of MT6227
External Memory Access
To allow external access, The MT6227 outputs 26bits(A25~A0) of address line along with 8 selection
signals that correspond to associated memory blocks. This is, MT6227 can support up to 8 MCU
