Exar XRT73L04, Manual

Page: 4 / 65

XRT73L04A
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.3
I
TABLE OF CONTENTS
G
ENERAL DESCRIPTION
......................................................................................................... 1
F
EATURES
.................................................................................................................................................... 1
APPLICATIONS ......................................................................................................................................... 1
Figure 1.XRT73L04A Block Diagram ................................................................................................................ 1
T
YPICAL
A
PPLICATIONS
................................................................................................................................. 2
Figure 2.MultiChannel ATM Application ............................................................................................................ 2
Figure 3.MultiService - Frame Relay Application .............................................................................................. 2
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
: ..................................................................................................... 2
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
: ....................................................................................................... 2
Figure 4.Pin out of the XRT73L04A in the 144 Pin TQFP package .................................................................. 3
O
RDERING INFORMATION
....................................................................................................... 3
TABLE OF CONTENTS ....................................................................................................... I
P
IN
D
ESCRIPTIONS
(
BY FUNCTION
) ......................................................................................... 4
T
RANSMIT
I
NTERFACE
................................................................................................................................... 4
R
ECEIVE
I
NTERFACE
..................................................................................................................................... 6
C
LOCK
I
NTERFACE
........................................................................................................................................ 7
O
PERATING
M
ODE
S
ELECT
........................................................................................................................... 8
C
ONTROL AND
A
LARM
I
NTERFACE
................................................................................................................. 9
M
ICROPROCESSOR
I
NTERFACE
.................................................................................................................... 11
P
OWER AND
G
ROUND
P
INS
......................................................................................................................... 13
N
O
C
ONNECTION
P
INS
................................................................................................................................ 14
E
LECTRICAL CHARACTERISTICS
........................................................................................... 15
A
BSOLUTE
M
AXIMUM
R
ATINGS
.................................................................................................................... 15
DC Electrical Characteristics .......................................................................................................... 15
AC Electrical Characteristics (See Figure 5) ........................................................................................................ 16
Terminal Side Timing Parameters (See Figure 6 and Figure 7) -- {(n) = 0, 1, 2 or 3 } ......................................... 16
Figure 5.Transmit Pulse Amplitude Test Circuit for E3, DS3 and STS-1 Rates (typical channel) .................. 17
Figure 6.Timing Diagram of the Transmit Terminal Input Interface ................................................................. 17
Figure 7.Timing Diagram of the Receive Terminal Output Interface ............................................................... 17
Line Side Parameters E3 Application ................................................................................................................... 18
Transmit Characteristics (see Figure 5) ............................................................................................................... 18
Line Side Parameters Sonet STS-1 Application ................................................................................................... 19
Transmit Characteristics (See Figure 5) ............................................................................................................... 19
Line Side Parameters DS3 Application ................................................................................................................ 20
Transmit Characteristics (see Figure 5) ............................................................................................................... 20
Figure 8.ITU-T G.703 Transmit Output Pulse Template for E3 Applications .................................................. 21
Figure 9.Bellcore GR-499-CORE Transmit Output Pulse Template for DS3 Applications ............................. 21
Figure 10.Bellcore GR-253-CORE Transmit Output Pulse Template for SONET STS-1 Applications ........... 22
Figure 11.Microprocessor Serial Interface Data Structure .............................................................................. 22
Microprocessor Serial Interface Timing (See Figure 12) ...................................................................................... 23
Figure 12.Timing Diagram for the Microprocessor Serial Interface ................................................................. 23
SYSTEM DESCRIPTION .................................................................................................. 24
T
HE
T
RANSMIT
S
ECTION
- C
HANNELS
0, 1, 2,
AND
3 .................................................................................... 24
T
HE
R
ECEIVE
S
ECTION
- C
HANNELS
0, 1, 2
AND
3 ....................................................................................... 24
T
HE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
................................................................................................. 24
Table 1:Role of Microprocessor Serial Interface pins when the XRT73L04A is operating in the Hardware Mode
24
Figure 13.Functional Block Diagram of the XRT73L04A ................................................................................ 25