Eurotech CPU-1450, Manual, Page: 32 / 43

Soft Power Management Registers 32
Super I/O Configuration D Register (SIOCFD)
Location Index 2Dh
Type Varies per bit
Battery-backed register
Name Address Function
Configuration D
Register Indexed 2Dh.
Index/data pair register address is 2E/2Fh. Power Management Control/Status Register. Used to set
ACPI mode for Super I/O chip .
Figure 7. PC87364 Super I/O interesting registers
Bit 7 6 5 4 3 2 1 0
Name
LED
Polarity
Control Last
PSON
State
PSON
Polarity
Crowbar Timeout
Resume
Last
PSON
State
Power
Supply Off
Power
Button
Mode
Reset 0 0
Strap
1 1 0 0 0
Bit Description
7 LED Polarity Control. This is a R/W bit. It determines if the LED outputs are active high or active low when they
are lit.
0: Active high (default at V
SB
power-up reset)
1: Active low
6 Last Power Supply On State. This is a RO bit. When operating in Legacy mode (bit 0 of this register is set to 0),
this bit reflects the state of the PSON pin sampled during the last power failure (no V
SB
), regardless of the polarity
of PSON.
0: Off
1: On
5 Power Supply On Polarity. This is a RO bit. The polarity of PSON is determined during V
SB
power-up by the
PSONPOL strap.
4-3 Crowbar Timeout. This is a R/W bit.
Bits
5 4 Value (Seconds)
0 0 0.4 to 0.9 (typical 0.6)
0 1 0.9 to 1.4 (typical 1.1)
1 0 1.4 to 1.9 (typical 1.6)
1 1 1.9 to 2.5 (typical 2.1) (default at V
PP
power-up reset)
Note that for any specific condition, there is a minimum gap of 0.25 seconds between the actual high limit of a
timeout setting and the low limit of the next time-out setting.
2 Resume Last Power Supply On State. This is a R/W bit. When it is set to 1, PSON resumes its last state, sampled
during the last power failure, after power returns. When this bit is set to 0, the PSON state is determined by the
SLPS3 state.
0: SLPS3 (default at V
PP
power-up reset)
1: Last PSON state. For correct operation, the system’s ACPI controller must be configured to resume to OFF.
This enables the power supply control logic to know the state of the chipset ACPI state machine after power
failure (no V
DD
and V
SB
).
1 Power Supply Off. This is a R/W bit. It always returns 0 when read. When using Legacy mode (bit 0 is set to 0)
and setting this bit to 1, this bit inactivates the PSON output, thereby shutting off the power supply.
0: No action (default at V
PP
power-up reset)
1: Inactivate PSON in Legacy mode
0 Power Button Mode. This is a R/W bit.
0: Legacy (default at V
SB
power-up reset)
1: ACPI
An0065. CPU-1450 Soft Power Management
Table 15. Super I/O Configuration D Register (SIOCFD)