Eurotech CPU-1450, Manual, Page: 10 / 43

CPU-1450 SPM block diagram architecture 10
PWRBTN#
Low Voltage
Intel Celeron Processor
Intel 82815
GMCH
Intel 82801
ICH2
PC133 SDRAM
On Board 256MB
PCI
LP
C
National Instrument
PC87364
Super IO
+3V3SB
+5VSB
PCI to ISA
bridge
ISA
LTC1536
PWRBTN#
JPR2
Default 1-2
PSON#
J9
Keyboard
Mouse
Parallel
Port
Serial 1
and 2
VGA
Ethernet
10/100Mb
AC97
USB
4 port
IDE
Ultra ATA
SLP_S3#
SLP_S5#
PWROK
+
RTC
PWBTOUT
+5VSB
PWRBTN #
+
Processor
Module
Celeron
Carrier PIII
+5V
+5V
+5V
3V3
3V3
Figure 2. CPU-1450 Block Diagram
The colours used in the previous diagram show the different power lines used to supply peripherals during
different power states. The chipset can easily understand the wake-up source.
A good point of start, to better understand the Power Management capabilities, is to refer directly to the
chipset datasheet; consider that the CPU-1450 architecture is developed with the support for APM-based
legacy power management for non ACPI implementations, it is not possible to refer exactly to the previous
chipsets data sheets without considering some restrictions based on the hardware choices made.
An0065. CPU-1450 Soft Power Management
The following section is intended to describe some restrictions the user needs to understand regarding the
CPU-1450.