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Schematic Diagrams
B - 4 Processor 1/7
B.Schematic Diagrams
Processor 1/7
PLACE NEAR U29
T H E R M_ V O L T 3 6
3
2
1
3 . 3 V
P E G_ I R C O MP _R
E XP _R B I A S
R 1 42
* 10 m i l _s h o r t
C R I T _T E M P _ R E P # 2 5
Analog Thermal Sensor
C 5 19
* . 1 U _ 1 0 V _ X 7 R _ 0 4 _+ U
C 1 44
* . 1 U _ 1 0 V _ X 7 R _ 0 4 _+ U
R 4 1 0
7 5 0_ 1 % _ 0 4
C 5 32
* . 1 U _ 1 0 V _ X 7 R _ 0 4 _+ U
C 5 33
* . 1 U _ 1 0 V _ X 7 R _ 0 4 _+ U
R 4 0 8
4 9 . 9_ 1 % _ 0 4
C 1 18
* . 1 U _ 1 0 V _ X 7 R _ 0 4 _+ U
C 1 19
* . 1 U _ 1 0 V _ X 7 R _ 0 4 _+ U
C 1 39
* . 1 U _ 1 0 V _ X 7 R _ 0 4 _+ U
C 1 07
* . 1 U _ 1 0 V _ X 7 R _ 0 4 _+ U
C 1 05
* . 1 U _ 1 0 V _ X 7 R _ 0 4 _+ U
C 5 18
* . 1 U _ 1 0 V _ X 7 R _ 0 4 _+ U
C 5 27
* . 1 U _ 1 0 V _ X 7 R _ 0 4 _+ U
C 1 41
* . 1 U _ 1 0 V _ X 7 R _ 0 4 _+ U
C 5 20
* . 1 U _ 1 0 V _ X 7 R _ 0 4 _+ U
C 1 14
* . 1 U _ 1 0 V _ X 7 R _ 0 4 _+ U
P
C
I E
XPR
ESS
--
GR
APH
ICS
D
MI
I
nt
el(
R) FDI
U 2 8A
G 9 89 P I N U P G A
D MI _ R X# [ 0 ]
A 2 4
D MI _ R X# [ 1 ]
C 2 3
D MI _ R X# [ 2 ]
B 2 2
D MI _ R X# [ 3 ]
A 2 1
D MI _ R X[ 0 ]
B 2 4
D MI _ R X[ 1 ]
D 2 3
D MI _ R X[ 2 ]
B 2 3
D MI _ R X[ 3 ]
A 2 2
D MI _ T X #[ 0]
D 2 4
D MI _ T X #[ 1]
G 2 4
D MI _ T X #[ 2]
F 2 3
D MI _ T X #[ 3]
H 2 3
D MI _ T X [ 0 ]
D 2 5
D MI _ T X [ 1 ]
F 2 4
D MI _ T X [ 3 ]
G 2 3
D MI _ T X [ 2 ]
E 2 3
F D I _ TX # [ 0 ]
E 2 2
F D I _ TX # [ 1 ]
D 2 1
F D I _ TX # [ 2 ]
D 1 9
F D I _ TX # [ 3 ]
D 1 8
F D I _ TX # [ 4 ]
G 2 1
F D I _ TX # [ 5 ]
E 1 9
F D I _ TX # [ 6 ]
F 2 1
F D I _ TX # [ 7 ]
G 1 8
F D I _ TX [ 0 ]
D 2 2
F D I _ TX [ 1 ]
C 2 1
F D I _ TX [ 2 ]
D 2 0
F D I _ TX [ 3 ]
C 1 8
F D I _ TX [ 4 ]
G 2 2
F D I _ TX [ 5 ]
E 2 0
F D I _ TX [ 6 ]
F 2 0
F D I _ TX [ 7 ]
G 1 9
F D I _ F S Y N C [ 0 ]
F 1 7
F D I _ F S Y N C [ 1 ]
E 1 7
F D I _ I N T
C 1 7
F D I _ LS Y N C [ 0 ]
F 1 8
F D I _ LS Y N C [ 1 ]
D 1 7
P E G _ I C O MP I
B 2 6
P E G_ I C OM P O
A 2 6
P E G _ R B I A S
A 2 5
P E G _ R C OM P O
B 2 7
P E G _ R X # [ 0 ]
K 3 5
P E G _ R X # [ 1 ]
J 3 4
P E G _ R X # [ 2 ]
J 3 3
P E G _ R X # [ 3 ]
G 35
P E G _ R X # [ 4 ]
G 32
P E G _ R X # [ 5 ]
F 3 4
P E G _ R X # [ 6 ]
F 3 1
P E G _ R X # [ 7 ]
D 35
P E G _ R X # [ 8 ]
E 3 3
P E G _ R X # [ 9 ]
C 33
P E G _ R X # [ 1 0 ]
D 32
P E G _ R X # [ 1 1 ]
B 3 2
P E G _ R X # [ 1 2 ]
C 31
P E G _ R X # [ 1 3 ]
B 2 8
P E G _ R X # [ 1 4 ]
B 3 0
P E G _ R X # [ 1 5 ]
A 3 1
P E G _R X [ 0 ]
J 3 5
P E G _R X [ 1 ]
H 34
P E G _R X [ 2 ]
H 33
P E G _R X [ 3 ]
F 3 5
P E G _R X [ 4 ]
G 33
P E G _R X [ 5 ]
E 3 4
P E G _R X [ 6 ]
F 3 2
P E G _R X [ 7 ]
D 34
P E G _R X [ 8 ]
F 3 3
P E G _R X [ 9 ]
B 3 3
P E G _ R X [ 1 0 ]
D 31
P E G _ R X [ 1 1 ]
A 3 2
P E G _ R X [ 1 2 ]
C 30
P E G _ R X [ 1 3 ]
A 2 8
P E G _ R X [ 1 4 ]
B 2 9
P E G _ R X [ 1 5 ]
A 3 0
P E G _ T X # [ 0 ]
L 3 3
P E G _ T X # [ 1 ]
M 35
P E G _ T X # [ 2 ]
M 33
P E G _ T X # [ 3 ]
M 30
P E G _ T X # [ 4 ]
L 3 1
P E G _ T X # [ 5 ]
K 3 2
P E G _ T X # [ 6 ]
M 29
P E G _ T X # [ 7 ]
J 3 1
P E G _ T X # [ 8 ]
K 2 9
P E G _ T X # [ 9 ]
H 30
P E G _T X # [ 1 0 ]
H 29
P E G _T X # [ 1 1 ]
F 2 9
P E G _T X # [ 1 2 ]
E 2 8
P E G _T X # [ 1 3 ]
D 29
P E G _T X # [ 1 4 ]
D 27
P E G _T X # [ 1 5 ]
C 26
P E G_ T X [ 0 ]
L 3 4
P E G_ T X [ 1 ]
M 34
P E G_ T X [ 2 ]
M 32
P E G_ T X [ 3 ]
L 3 0
P E G_ T X [ 4 ]
M 31
P E G_ T X [ 5 ]
K 3 1
P E G_ T X [ 6 ]
M 28
P E G_ T X [ 7 ]
H 31
P E G_ T X [ 8 ]
K 2 8
P E G_ T X [ 9 ]
G 30
P E G _ T X [ 1 0 ]
G 29
P E G _ T X [ 1 1 ]
F 2 8
P E G _ T X [ 1 2 ]
E 2 7
P E G _ T X [ 1 3 ]
D 28
P E G _ T X [ 1 4 ]
C 27
P E G _ T X [ 1 5 ]
C 25
Q4 4
2 N 3 9 0 4
B
E
C
C 5 29
* . 1 U _ 1 0 V _ X 7 R _ 0 4 _+ U
U 2 9
W 8 3L 7 7 1 A W G
V D D
1
D +
2
D -
3
T H E R M
4
G N D
5
A L E R T
6
S D A T A
7
S C L K
8
C 5 30
* . 1 U _ 1 0 V _ X 7 R _ 0 4 _+ U
3. 3 V
D MI _ T X P 2
2 2
D MI _ T X P 1
2 2
D MI _ T X P 0
2 2
D MI _ T X N 2
2 2
D MI _ T X N 1
2 2
D MI _ T X N 0
2 2
D MI _ T X P 3
2 2
D M I _ R XN 2
2 2
D M I _ R XN 1
2 2
D M I _ R XN 0
2 2
D MI _ T X N 3
2 2
D M I _ R XP 2
2 2
D M I _ R XP 1
2 2
D M I _ R XP 0
2 2
D M I _ R XN 3
2 2
F D I _ I N T
2 2
F D I _ F S Y N C 1
2 2
F D I _ F S Y N C 0
2 2
D M I _ R XP 3
2 2
P E G _ R X # 2 1 3
F D I _ L S Y N C 1
2 2
F D I _ L S Y N C 0
2 2
P E G _ R X 7 1 3
P E G _ R X # 4 1 3
P E G _ R X 5 1 3
P E G _ R X # 7 1 3
P E G _ R X # 1 1 3
P E G _ R X 4 1 3
P E G _ R X # 0 1 3
P E G _ R X # 3 1 3
P E G _ R X 2 1 3
P E G _ R X # 6 1 3
P E G _ R X 3 1 3
P E G _ R X # 5 1 3
P E G _ R X 6 1 3
P E G _ R X 0 1 3
P E G _ TX 3
1 3
P E G _ TX 6
1 3
P E G _ R X 1 1 3
P E G _ TX # 3 1 3
P E G _ TX 0
1 3
P E G _ TX # 2 1 3
P E G _ TX # 5 1 3
P E G _ TX 7
1 3
P E G _ TX 4
1 3
P E G _ TX # 7 1 3
P E G _ TX 1
1 3
P E G _ TX # 0 1 3
P E G _ TX 5
1 3
P E G _ TX # 1 1 3
P E G _ TX 2
1 3
P E G _ TX # 6 1 3
F D I _ TX N 1
2 2
F D I _ TX N 0
2 2
P E G _ TX # 4 1 3
F D I _ TX N 5
2 2
F D I _ TX N 4
2 2
F D I _ TX N 3
2 2
F D I _ TX N 2
2 2
F D I _ TX P 1
2 2
F D I _ TX P 0
2 2
F D I _ TX N 7
2 2
F D I _ TX N 6
2 2
F D I _ TX P 5
2 2
F D I _ TX P 4
2 2
F D I _ TX P 3
2 2
F D I _ TX P 2
2 2
V D D 3
2 0 , 3 3, 36 , 3 7 , 3 8 , 4 5
3 . 3 V
4, 1 2 , 1 3 , 2 0 , 21 , 2 2 , 2 4 , 2 5 , 27 , 2 9 , 3 0 , 3 1, 32 , 3 3 , 3 4 , 3 7, 3 9 , 4 0 , 4 1
F D I _ TX P 7
2 2
F D I _ TX P 6
2 2
20 mil
T H E R M _ A L E R T# 3 6
D 8
*R B 7 51 V
A
C
1:2 (4mils:8mils)
P M _ E X T TS # _E C 4
On Board DDR3 Thermal Sensor
PROCESSOR 1/7 ( DMI,PEG,FDI )
It applies to Auburndale and Clarksfield discrete graphic designs.
If discrete graphic chip is used for Auburndale, VAXG (GFX core) rail can be connected
to GND if motherboard only supports discrete graphics and also in a common
motherboard design if GFX VR is not stuffed. On the other hand, if the VR is stuffed,
VAXG can be left floating in a common motherboard design (Gfx VR keeps VAXG from
floating).
In addition, FDI_RXN_[7:0] and FDI_RXP_[7:0] can be left floating on the PCH.
FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Auburndale.
The GFX_IMON, FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and
FDI_INT signals should be tied to GND (through 1K ? % resistors) in the common
motherboard design case. Please not that if these signals are left floating, there are no
functional impacts but a small amount of power (~15 mW) maybe wasted. VAXG_SENSE
and VSSAXG_SENSE on Auburndale can be left as no connect.
DPLL_REF_SSCLK and DPLL_REF_SSCLK# can be connected to GND on Auburndale
directly if motherboard only supports discrete graphics. In a common motherboard
design, these pins are driven via PCH (even if Graphics is disabled by BIOS) thus no
external termination is required.
PULL HIGH? ? ?
IBEX? PAGE21
C 5 8 1
*. 1 U _1 6 V _ 0 4
C 5 8 9
. 1U _ 1 6V _0 4
C 59 3
. 1 U _1 6 V _ 0 4
Q6 8
G 7 1 1S T9 U
OU T
1
V C C
2
G N D
3
S M C _ C P U _ T H E R M
2 1 , 3 6
S M D _ C P U _ T H E R M
2 1 , 3 6
P E G _ T X _2
P E G _ T X _1
P E G _ T X #_ 3
P E G _ T X _4
P E G _ T X #_ 2
P E G _ T X #_ 5
P E G _ T X #_ 7
P E G _ T X _6
P E G _ T X #_ 6
P E G _ T X #_ 1
P E G _ T X #_ 4
P E G _ T X _7
P E G _ T X #_ 0
P E G _ T X _0
P E G _ T X _5
P E G _ T X _3
Sheet 3 of 55
Processor 1/7
Summary of Contents for M770CU
Page 1: ......
Page 2: ......
Page 3: ...Preface I Preface Notebook Computer M770CU M775CU W760CU W765CU Service Manual...
Page 24: ...Introduction 1 12 1 Introduction...
Page 46: ...Disassembly 2 22 2 Disassembly...
Page 54: ...Part Lists A 8 LCD M770CU M775CU A Part Lists LCD M770CU M775CU Figure A 6 LCD M770CU M775CU...
Page 62: ...Part Lists A 16 LCD W760CU W765CU A Part Lists LCD W760CU W765CU Figure A 14 LCD W760CU W765CU...