Picolo Tetra Product Description
11
5.
Picolo Tetra block diagram
Picolo Tetra Block Diagram
MIO LINK
PC reset
headers
PCI control
PIO
Para
lle
l
in
te
rf
ace
Vid
eo
Co
mm
on-
m
ode n
o
is
e
rem
o
va
l
C
onnect
ors on
bracke
t
VID 1
VID 2
VID 3
VID 4
Transparent
PCI bridge
64 bits, 66 MHz
Digital IO
VEB LINK
(video in)
VEB LINK
(video out)
Elec
tr
o
m
a
gne
tic
c
o
mp
at
ibi
lit
y ne
tw
ork
PCI connector
FIFO buffer 1
630 bytes
PCI
inter
fac
e
with color decoding,
scaling,
format conversion
Digitizer 1
PCI
int
er
fac
e
FIFO buffer 2
630 bytes
with color decoding,
scaling,
format conversion
Digitizer 2
FIFO buffer 3
630 bytes
PCI
in
te
rf
ace
with color decoding,
scaling,
format conversion
Digitizer 3
FIFO buffer 4
630 bytes
PCI
in
te
rf
ace
with color decoding,
scaling,
format conversion
Digitizer 4
1
2
3
Q
uadr
uple
4-
to
-1
analog r
ou
ter
E
m
bedde
d P
C
I b
u
s
Video input/output routing
The detailed routing is presented in part V, “VEB and VEB12 Product Description”.
