ETAS XETK-V1.0, User Manual, Page: 47 / 71

XETK-V1.0 - User’s Guide 47
ETAS Technical Data
7.10 Switching Characteristics
The following diagrams show the timings the XETK-V1.0 can process.
7.10.1 Read Timing: Data Emulation and Measurement Data DPR
Fig. 7-1 Read Cycle: Data Emulation and Measurement Data DPR
7.10.2 Write Timing: Data Emulation and Measurement Data DPR
.
Fig. 7-2
Write Cycle: Data Emulation and Measurement Data DPR
Note
All timings are measured at a reference level of 1.5 V. Output signals are mea-
sured with 10 pF to ground and 50

to 1.5 V.
Para. Description Min Max Unit
t
1
Address access time 20 ns
t
2
Chip select access time 24 ns
t
3
Output enable until valid data is driven to bus 24 ns
t
4
Valid data is driven to bus after output enable
inactive 1 ns
t
5
Time after read until other device may drive bus 14 ns
Para. Description Min Max Unit
t
1
Address valid before write enable becomes active 4 ns
t
2
Address valid before end of write 16 ns
t
3
Address valid after end of write 8 ns
0ns 5ns 10ns 15ns 20ns 25ns 30ns 35ns 40ns
ADDR[12:30]
CS[3:0]
OE
DATA[15:0]
Address
Data
t1
t2
t3
t4
t5
0ns 5ns 10ns 15ns 20ns 25ns 30ns 35ns 40ns
ADDR[12:30]
CS[3:0]
RD/WR
WE[1:0]
DATA[15:0]
Address
Data
t1
t2
t3
t4 t5
t6