ETAS
Technical Data
XETK-S30.0 - User’s Guide
37
7.7
Microcontroller Interface
7.8
Test Characteristics
Symbol
Condition
Min
Typ
Max Unit
ECU Standby
RAM Output Volt-
age (1.25 V
selected)
VDDSTBY max 500 mA load 1.19
1.25 1.31 V
ECU Standby
RAM Output Volt-
age (1.30 V
selected)
VDDSTBY max 500 mA load 1.23
1.3
1.34 V
VDDPSTBY
Output Voltage
VDDP-
STBY
max 80 mA load 3.14
3.3
3.46 V
Cal_Wakeup
Output Voltage
CAL_WAK
EUP
U
Batt
= 6 - 36 V;
load = 0 - 50 mA
U
Batt
-1V
U
Batt
V
ECU Power Sup-
ply Supervision
Voltage
(3.3 V selected)
VDDP
ECU on
2.48
2.58 2.68 V
ECU off
2.33
2.43 2.53 V
IDDP
VDDP 3.3 V
200
A
ECU Power Sup-
ply Supervision
Voltage
(5.0 V selected)
VDDP
ECU on
2.98
3.08 3.18 V
ECU off
2.83
2.93 3.03 V
IDDP
VDDP 5.0 V
300
A
ECU Standby
RAM Supervision
Voltage
(1.25 V selected)
VDDSTBY
/VDDST-
BY_SENSE
VDDSTBY
1.02
1.12 1.22 V
VDDSTBY
1
1.1
1.2
V
IDDSTBY
VDDSTBY 1.25 V
73
A
Parameter
Symbol Condition
Min Typ
Max Unit
Reset delay 1
1)
t
Reset1
U
Batt
= 12 V
VDDP = 0 V
3.3 V/
5.0 V
without transferring
FPGA
29
40
ms
Reset delay 2
2)
t
Reset2
U
Batt
= 0 V
12 V
transfer FPGA
200
340 ms
1)
Delay of ECU reset through ETK without transferring the FPGA (U
Batt
pres-
ent, VDDP will be switched on)
2)
max. delay of ECU reset through ETK (U
Batt
and VDDP will be switched on)
