ETAS
Technical Data
BR_XETK-S3.0
-
User Guide
52
7.8
Power-on Delay of ECU Reset
7.9
DAP Timing Characteristics
The BR_XETK-S3.0 supports two DAP modes:
• 2-pin DAP mode: one data pin (direction via protocol), one clock pin
• 3-pin DAP mode: two data pins (bidirectional, direction via protocol), one
clock pin
The 2-pin DAP mode is the BR_XETK-S3.0 DAP interface default mode.
7.9.1
2-Pin DAP Mode
Fig.
7
-
2
2-Pin DAP Mode Timing
Parameter
Symbol Condition
Min Typ
Max Unit
Reset delay 1
1)
t
Reset1
U
Batt
= 12
V
ECU_VDDP goes
high
3
5
20
ms
Reset delay 2
2)
t
Reset2
U
Batt
goes high
100
240 ms
1)
Delay of ECU reset through ETK without transferring the FPGA (U
Batt
pres
-
ent, VDDP will be switched on)
2)
max. delay of ECU reset through ETK (U
Batt
and VDDP will be switched on)
NOTE
DAP timing parameters in this chapter refer to the DAP interface (CON2) of
the BR_XETK-S3.0. The DAP wiring to the ECU (ETAM8) must be taken
account additionally.
All timings are measured at a reference level of 1.5 V.
Parameter
Symbol
Value [ns]
Comment
DAP0 Clock Period (typ.)
(ETK --> Target)
t
CLK
10
100 MHz DAP Clock Fre
-
quency
20
50 MHz DAP Clock Fre
-
quency
DAP1 Set-Up Time
(ETK --> Target)
t
SU
4
DAP1 Hold Time
(ETK --> Target)
t
H
2
DAP1 Clock-to-Out Time
(Target --> ETK)
t
CO
~
Undetermined, ETK auto
-
matically determines
optimum sampling point
DAP0_(ETK)
DAP1, DAP2_(ETK)
DAP1, DAP2_(ECU)
t
SU
t
H
t
CLK
t
CO
t
Valid
