BIOS SETUP
TF-486 / 38
PCI IDE IRQ Map to : The PCI IDE interface in the chipset has two channels, it requires
two interrupt services. The primary and secondary IDE INT# fields default to values
appropriate for two IDE channels, with the primary PCI IDE channel having a lower
interrupt than the secondary.
CPU to PCI Write Buffer : When Enable, the CPU can write up to four dwords of data to
the PCI write buffer before the CPU must wait for the PCI bus cycles to finish. When
Disabled, the CPU must wait after each write cycle until the PCI bus signals that it is
ready to receive more data.
CPU to PCI Byte Merge : Byte merging permits merging of the data in consecutive
CPU-to-PCI byte / word writes with the same dword address, into the same posted write
buffer location. The merged collection of bytes is then sent over the PCI Bus as a
single dword. Byte merging is performed in the compatible VGA range only (0A0000-
0BFFFF)
PCI to DRAM Buffer : The system supports buffered writes from the PCI bus to DRAM
for greater efficiency.