BIOS SETUP
TF-486 / 34
AT-BUS Clock : You can set the speed of the AT bus in terms of the CPU clock speed,
or at the fixed speeds of 7.16M Hz.
DRAM Read / Write Timing : Timing that the system uses when reading from and
writing to DRAM. Do not reset from the manufacturer default value.
SRAM Reading Timing : These SRAM timing numbers are the pattern of cycles the
CPU uses to read data from the cache. Do not reset this option from its default.
SRAM Writing Timing : If necessary, you can insert a wait state in the SRAM write
cycle.
Hidden Refresh : When Disabled, DRAM is refreshed by IBM AT methodology, using a
CPU cycles for each refresh. When hidden refresh is Enabled, the DRAM controller
seeks the most opportune moment for a refresh, regardless of CPU cycles, with least
disruption of system activity and least performance penalty. Hidden refresh is faster
and more efficient, and it also allows the CPU to maintain the status of the DRAM even if
the system goes into a power management “suspend” mode.
Memory Holes (15M-16M) : The default setting is “Disable”. Set to “Enable” means
that when the system memory size is equal to or greater than 16M bytes, the physical
memory address from 15M to 16M will be passed to PCI or ISA and there will be 1M
Bytes hole in your system memory. This option is designed for some OS with special
add-on cards which need 15M-16M memory space.
ISA I/O Recovery : The CPU and local bus are much faster than industry standard
architecture (ISA) input / output (I/O) bus. Select Enabled to allow additional time for
I/O devices to respond to the system. Otherwise, data could be lost. If all your I/O
devices are capable of fast I/O, selecting Disabled can speed up processing.
Fast-Back-to-Back : When Enable, consecutive write cycles targeted to the same slave
become fast back-to-back on the PCI bus.
Special Functions Port : Select Touch Screen I/O ports address.
Touch Controller IRQ : Select Touch Screen IRQ.