8.4.
Timer-Status-Register
Read / Write BaseA16
bit 31
Global-Interrupt-enable
bit 30
IO-Interrupt-Enable
bit 29
Watchdog-Enable
bit 28
Timer-Enable
bit 27
Timer-Status (IRQ by the timer) read only !
bit 26
Watchdog-Status (IRQ by WD) read only !
bit 25
Input-Status (IRQ by input signal) read only !
bit 24
Configuration of the card
bit 23 - 16
not used
bit 15 - 0
Timer-Value (>0)
By the “Global-Interrupt-Enable-bit” the interrupts can made activ or not activ.
Attention must be paid that for enabling interrupts. Not only the “Global-Interrupt-
Enable-Bit” must be set but also the “Interrupt-Enable-Bit” of the PCI-Target-Con-
troller !
The bits “Timer-Enable” and “Input-Enable” are used to activate the timer respec-
tively the watchdog.
The 3 bits for the status are indicating which function has generated an interrupt.
The “Configuration-bit” is used to recognize the used IO card.
“Configuration-Bit” = 0 means model IO 1388/ 0 ( 16 input / output channels),
“Configuration-bit” = 1 model IO 1388/1 (32 input / output channels).The bits 24
- 16 should be set to “0".
The bits 15 - 0 are used to programm the timer. The value must be 1 or higher.
The measuring rate is:
f = 20 kHz/ (timer value)
Attention! The shortest measuring rate is determined by the used system,
because Windows is not real time capable. The timer can be disabled by the
“Timer-Enable-Bit” or the “Global-Interrupt-Enable-Bit”.
8. Registers of the card IO 1388
13
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