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S5U13T04P00C100 Evaluation Board User Manual
XA3A-G-001-00
Revision 1.0
Issue Date: 2013/03/15
Seiko Epson Corporation
3 Setup and Configuration
The main functional blocks of the evaluation board are shown below.
Figure 3-1 S5U13T04P00C100 Reference Board Block Diagram
CNF0 is configured with jumpers JP3 and JP4 as shown in the following table.
Table 3-1 CNF0 Configuration Selection
CNF0
JP3
JP4
Comments
0
Open
Short
H_RDY signal is all ways driven (Default)
1
Short
Open
H_RDY signal is open drain signal
S1D13T04
J3
Host
I/F
U1
Reserved
For Testing
J4
Panel
I/F
J1
2.0 Inch
EPD
Panel
Power
J2
JP2
HVDD
Q1
JP1
RVDD
CNF0
JP3/JP4
SVT13T04 board