Epson S5U13705B00C User Manual Download

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S5U13705B00C Rev 2.0 PCI Evaluation Board

Seiko Epson Corporation

Rev. 3.1

Table of Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Configuration DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1 CPU Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 CPU Bus Connector Pin Mapping . . . . . . . . . . . . . . . . . . . . . . 14

5 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

9 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

10 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

11 Change Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

12 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Summary of Contents for S5U13705B00C

Page 1: ...Rev 3 1 S1D13705 Embedded Memory LCD Controller S5U13705B00C Rev 2 0 Evaluation Board User Manual Document Number X27A G 014 03 1 ...

Page 2: ...xport and or to otherwise dispose of the products and any technical information furnished if any for the devel opment and or manufacture of weapon of mass destruction or for other military purposes All brands or product names mentioned herein are trademarks and or registered trademarks of their respective companies SEIKO EPSON CORPORATION 2001 2018 All rights reserved Evaluation Board Kit and Deve...

Page 3: ...nector Pin Mapping 14 5 LCD Interface Pin Mapping 16 6 Technical Description 17 6 1 PCI Bus Support 17 6 2 Direct Host Bus Interface Support 17 6 3 S1D13705 Embedded Memory 17 6 4 Adjustable LCD Panel Positive Power Supply VDDH 17 6 5 Adjustable LCD Panel Negative Power Supply VLCD 18 6 6 Passive Active LCD Panel Support 18 6 7 Power Save Modes 18 6 8 Clock Options 19 7 Software 20 8 Parts List 21...

Page 4: ...4 Seiko Epson Corporation S5U13705B00C Rev 2 0 PCI Evaluation Board Rev 3 1 THIS PAGE LEFT BLANK ...

Page 5: ...ard The board is designed as an evaluation platform for the S1D13705 Embedded Memory LCD Controller This document is updated as appropriate Please check for the latest revision of this document before beginning any development The latest revision can be downloaded at vdc epson com We appreciate your comments on our documentation Please contact us via email at vdc documentation ea epson com ...

Page 6: ... Bus Interfaces Configuration options Adjustable positive LCD bias power supply from 23V to 40V Adjustable negative LCD bias power supply from 23V to 14V 4 8 bit 3 3V or 5V single monochrome or color passive LCD panel support 9 12 bit 3 3V or 5V active matrix TFT LCD panel support Software and hardware initiated power save mode Selectable clock source for bus clock and CLKI External oscillator for...

Page 7: ...th evaluation board and S1D13705 LCD controller to be configured for a specified evaluation platform 3 1 Configuration DIP Switches The S1D13705 has configuration inputs CNF 3 0 and BS input which are read on the rising edge of RESET In order to configure the S1D13705 for multiple Host Bus Inter faces a six position DIP switch SW1 is required The following figure shows the location of DIP switch S...

Page 8: ...made with JP3 Table 3 1 Configuration DIP Switch Settings Switch S1D13705 Signal Value on this pin at rising edge of RESET is used to configure Open Off 1 Closed On 0 SW1 3 1 CNF 2 0 Select host bus interface as follows CNF2 CNF1 CNF0 Host Bus Interface 0 0 0 SH 4 0 0 1 SH 3 0 1 0 Reserved 0 1 1 MC68K 1 1 0 0 Reserved 1 0 1 MC68K 2 1 1 0 Reserved 1 1 1 Generic 1 Generic 21 Note The host bus interf...

Page 9: ...te For PCI host JP1 can be set in either position Figure 3 2 Configuration Jumper JP1 Location Table 3 2 Jumper Summary Jumper Function Position 1 2 Position 2 3 No Jumper JP1 IOVDD Selection 3 3V IOVDD 5 0V IOVDD n a JP2 Bus Clock Selection External Oscillator U7 From Host CPU n a JP3 BS Signal Selection Pulled Down to GND for Generic 1 Interface Pulled High to IOVDD for Generic 2 Interface For S...

Page 10: ...may be used for non PCI host Figure 3 3 Configuration Jumper JP2 Location JP3 BS Signal Selection JP3 is used to pull up or down BS input of S1D13705 for selection of Generic 1 or Generic 2 interface When the jumper is in position 1 2 BS is pulled down to select Generic 1 interface When the jumper is in position 2 3 BS is pulled high to IOVDD to select Generic 2 interface For SH 3 SH 4 MC68K 1 and...

Page 11: ...on 2 3 the voltage level is set to 5 0V Figure 3 5 Configuration Jumper JP4 Location JP5 PCI Bridge FPGA JP5 is used to enable or disable the PCI bridge FPGA When the jumper is in position 1 2 the PCI bridge FPGA is disabled This position must be used for non PCI host When the jumper is off the PCI bridge FPGA is enabled The jumper must not be present for PCI host Figure 3 6 Configuration Jumper J...

Page 12: ...P6 When the jumper is in position 1 2 LCDPWR signal to the panel is active low When the jumper is in position 2 3 LCDPWR signal to the panel is active high Figure 3 7 Configuration Jumper JP6 Location JP7 CLKI Selection JP7 selects the source for CLKI input on S1D13705 When the jumper is in position 1 2 CLKI signal is provided by external oscillator U2 When the jumper is in position 2 3 CLKI signa...

Page 13: ...hi SH 4 Motorola MC68K 1 Motorola MC68K 2 AB 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 AB0 A0 A0 A0 A0 LDS A0 DB 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 1 CS External Decode CSn CSn External Decode BCLK BCLK BCLK CKIO CKIO CLK CLK BS Connect to VSS Connect to IOVDD BS BS AS AS RD WR RD1 Connect to IOVDD RD WR RD WR R W R W RD RD0 RD RD RD Connect to IOVDD SIZ1 WE0 WE0 WE WE0 WE0 Connec...

Page 14: ...0 Connected to DB7 of the S1D13705 11 Ground 12 Ground 13 Connected to DB8 of the S1D13705 14 Connected to DB9 of the S1D13705 15 Connected to DB10 of the S1D13705 16 Connected to DB11 of the S1D13705 17 Ground 18 Ground 19 Connected to DB12 of the S1D13705 20 Connected to DB13 of the S1D13705 21 Connected to DB14 of the S1D13705 22 Connected to DB15 of the S1D13705 23 Connected to RESET of the S1...

Page 15: ... 10 Ground 11 Connected to AB8 of the S1D13705 12 Connected to AB9 of the S1D13705 13 Connected to AB10 of the S1D13705 14 Connected to AB11 of the S1D13705 15 Connected to AB12 of the S1D13705 16 Connected to AB13 of the S1D13705 17 Ground 18 Ground 19 Connected to AB14 of the S1D13705 20 Connected to AB15 of the S1D13705 21 Connected to AB16 of the S1D13705 22 Not connected 23 Not connected 24 N...

Page 16: ...it 4 bit 8 bit 8 bit 8 Bit 9 bit 12 bit BFPDAT0 1 driven 0 D0 LD0 driven 0 D0 B5 1 D0 G3 1 LD0 lR2 1 R2 R3 BFPDAT1 3 driven 0 D1 LD1 driven 0 D1 R5 1 D1 R3 1 LD1 lB1 1 R1 R2 BFPDAT2 5 driven 0 D2 LD2 driven 0 D2 G4 1 D2 B2 1 LD2 lG1 1 R0 R1 BFPDAT3 7 driven 0 D3 LD3 driven 0 D3 B3 1 D3 G2 1 LD3 lR1 1 G2 G3 BFPDAT4 9 D0 D4 UD0 D0 R2 1 D4 R3 1 D4 R2 1 UD0 uR2 1 G1 G2 BFPDAT5 11 D1 D5 UD1 D1 B1 1 D5 ...

Page 17: ...interfaces supported see CPU Interface on page 13 Note The PCI Bridge FPGA must be disabled using JP5 in order for direct host bus interface to operate properly 6 3 S1D13705 Embedded Memory The S1D13705 has 80K bytes of embedded SRAM The 80K byte display buffer address space is directly and contiguously available through the 17 bit address bus The S1D13705 registers are located in the upper 32 byt...

Page 18: ...pports 4 8 bit single and dual monochrome passive panels 4 8 bit single and dual color passive panels 9 12 bit TFT active matrix panels All the necessary signals are provided on the 40 pin LCD connector J5 For connection information refer to Table 5 1 LCD Signal Connector J5 on page 16 The buffered LCD connector J5 provides the same LCD panel signals as those directly from S1D13705 but with voltag...

Page 19: ... minimum input clock frequency A 6 0MHz oscillator U2 socketed is provided as the input clock source However depending on the LCD resolution desired frame rate and power consumption budget another clock frequency may be required A jumper JP7 is provided to allow CLKI input to be the same as BCLK input for systems in which is desired to use only one clock signal for both BCLK and CLKI The bus clock...

Page 20: ...tion Test utilities and display drivers are also available for the S1D13705 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13705CFG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifyin...

Page 21: ...r 12 1 J5 CON40A 0 1 20x2 0 025 sq shrouded header center key t h 13 1 L1 1uH RCD MCI 1812 inductor 1uH MT or MSI 1812 1uH MT 14 3 L2 L3 L4 Ferrite Bead Philips BDS3 3 8 9 4S2 15 1 Q1 MMBT3906 Generic MMBT3906 16 1 Q2 MMBT3904 Generic MMBT3904 17 13 R1 R6 R10 R11 R33 R36 R39 15K 5 1206 resistor 18 1 R8 0R 1206 resistor 0 ohms 19 1 R14 475K 1 1206 resistor 20 1 R15 200K Pot 200K Trim POT Spectrol 6...

Page 22: ...86 SO SO 14 74HCT86 36 1 U10 RD 0412 Xentek RD 0412 positive power supply 37 1 U11 EPN001 Xentek EPN001 negative power supply 38 1 U14 EPF6016TC144 2 Altera EPF6016TC144 2 39 1 U15 8 pin DIP socket Machined socket 8 pin 40 1 U15 EPC1441PC8 Altera EPC1441PC8 socketed 41 6 JP1 JP2 JP3 JP4 JP6 J P7 Jumper shunt for 0 1 header 42 1 Bracket Computer Bracket Blank PCI Keystone Cat No 9203 43 2 Scew Pan ...

Page 23: ... 74AHC04 SO 5 6 14 7 U8D 74AHC04 SO 9 8 14 7 U1 SED1375F0A 70 69 68 67 66 65 64 63 62 59 58 57 56 55 54 53 37 36 35 34 32 31 30 74 43 61 20 40 72 60 50 27 80 19 18 17 16 15 14 13 12 11 9 8 7 6 5 4 3 33 49 48 47 46 45 79 78 77 76 75 73 51 71 2 44 1 21 10 41 52 29 26 25 24 23 39 38 28 42 22 AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT5 FPDAT...

Page 24: ...P FPDAT 7 0 1 LCDPWR 1 3 nLCDPWR 3 FPDAT8 1 FPDAT9 1 FPDAT10 1 FPDAT11 1 FPSHIFT 1 DRDY 1 FPLINE 1 FPFRAME 1 VDDH VLCD 5V 5V 3 3V 12V JP6 HEADER 3 1 2 3 C12 10uF 25V R41 0R U5 74AHC244 2 18 4 16 6 14 8 12 11 9 13 7 15 5 17 3 1 19 20 10 1A1 1Y1 1A2 1Y2 1A3 1Y3 1A4 1Y4 2A1 2Y1 2A2 2Y2 2A3 2Y3 2A4 2Y4 1G 2G VCC GND J5 CON40A 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 1...

Page 25: ... PSVCC 5V 5V 5V 5V U9C 74HCT86 SO 9 10 8 14 7 C16 0 1uF C21 4 7uF 50V R18 10K R19 100K R20 100K Q2 MMBT3904 1 2 3 R14 475K R15 200K Pot 1 3 2 R16 14K C19 4 7uF 50V C20 4 7uF 50V C22 47uF 16V C23 56uF 35V Low ESR C18 47uF 16V R17 10K U9B 74HCT86 SO 4 5 6 14 7 R21 100K Pot 1 3 2 U10 RD 0412 1 2 3 4 5 6 7 8 9 10 11 12 VOUT_ADJ DC_IN REM O T E GND GND GND GND GND NC GND GND DC _OUT U11 EPN001 1 2 3 4 ...

Page 26: ...PCI B 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 52 53 54 55 56 57 58 59 60 61 62 12V TCK GND TDO 5V 5V INTB INTD PRSNT 1 RESERVED PRSNT 2 RESERVED GND CLK GND REQ VI O AD31 AD29 GND AD27 AD25 3 3V C BE3 AD23 GND AD21 AD19 3 3V AD17 C BE2 GND IRDY 3 3V DEVSEL GND LOCK PERR 3 3V SERR 3 3V C BE1 AD14 GND AD12 AD...

Page 27: ... 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 IO1 IO2 IO3 nCE GND Vccint Vccio IO8 IO9 IO10 IO11 IO12 IO13...

Page 28: ...Board Layout 28 Seiko Epson Corporation S5U13705B00C Rev 2 0 PCI Evaluation Board Rev 3 1 10 Board Layout ...

Page 29: ...rd S5U13705B00C Rev 2 0 PCI Evaluation Board Seiko Epson Corporation 29 Rev 3 1 11 Change Record X27A G 014 03 Revision 3 1 Issued March 26 2018 updated Sales and Technical Support Section updated some formatting ...

Page 30: ... Support For more information on Epson Display Controllers visit the Epson Global website https global epson com products_and_drivers semicon products display_controllers For Sales and Technical Support contact the Epson representative for your region https global epson com products_and_drivers semicon information support html ...

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