6. Appendix
6
EPSON
S1R72V18 Evaluation Board Manual
(Rev.1.01)
6. Appendix
6.1
Connection Example 1 (CPU I/F connection example)
A[8:1]
A[0]
D[15:0]
XCS
XRD
XWRH
XWRL
XDREQ_0
※
1
XDACK_0
※
2
XDREQ_1
※
1
XDACK_1
※
2
XINT
Address[8:1]
16-bit CPU (XWRH/XWRL) connection example
DATA[15:0]
XCS
XRD
XWRH
XWRL
XDREQ0
XDACK0
XDREQ1
XDACK1
XINT
*1: Open when DMA is not in use
*2: Disabled when DMA is not in use
A[8:1]
A[0]
D[15:0]
XCS
XRD
XWRH
XWRL
XDREQ_0
※
1
XDACK_0
※
2
XDREQ_1
※
1
XDACK_1
※
2
XINT
Address[8:1]
16-bit CPU (XBEH/XBEL) connection example
DATA[15:0]
XCS
XRD
XBEH
XWR
XDREQ0
XDACK0
XDREQ1
XDACK1
XINT
XBEL
*1: Open when DMA is not in use
*2: Disabled when DMA is not in use
CPU Board
S1R72V18 Evaluation Board
