Epson RX8111CE Applications Manual Download

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RX8111CE

Page

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ETM61E-01

14.3.3. Diagram of alarm interrupt function

Figure 22 Alarm interrupt block diagram

AIE bit

/INT output

AF bit

Event occurs

Internal operation

内部動作

Write operation

Figure 23 Alarm interrupt timing chart

AF Clear to 0

Internal second carry

DAY detection result

WEEK detection result

WEEK / DAY AE

HOUR detection result

HOUR AE

MIN detection result

MIN AE

SEC detection result

SEC AE

WADA

/INT

AIE

AF Flag

Summary of Contents for RX8111CE

Page 1: ...ETM61E 01 Preliminary Product name Product number RX8111CE A X1B000421000115 RX8111CE B X1B000421000215 Application Manual Real Time Clock Module RX8111CE ...

Page 2: ...general electronic applications and specifically designated applications Anticipated Purpose Epson products are NOT intended for any use beyond the Anticipated Purpose that requires particular quality or extremely high reliability in order to refrain from causing any malfunction or failure leading to critical harm to life and health serious property damage or severe impact on society including but...

Page 3: ...ETM61E Revision History Rev No Date Page Description 01 29 Jan 2020 Release ...

Page 4: ...y Software 13 11 Reference information 13 11 1 Reference Data 13 12 Application Notes 14 13 Overview of Functions and Description Of Registers 15 13 1 Overview Of Functions 15 13 2 Register Table 16 13 2 1 Register Table 16 13 3 Description Of Registers 20 13 3 1 Clock and Calendar Counter 10h 16h 20 13 3 2 Wake up Timer Down Counter 1Ah 1Ch 2Dh 20 13 3 3 Alarm Registers 17h 19h 20 13 3 4 Function...

Page 5: ... function 36 14 7 1 Description of Battery backup switchover function 36 14 7 2 Battery backup switchover related register 36 14 8 Time Stamp Function 41 14 8 1 Outline of Time Stamp function 41 14 8 2 Time Stamp related register 41 14 8 3 Time stamp function triggered by EVIN pin input 42 14 8 4 Time stamp function triggered by I2 C access 44 14 8 5 Time stamp stored register 45 14 8 6 RTC intern...

Page 6: ... is a real time clock module with integrated 32 768 kHz crystal oscillator and I2 C interface In addition to providing a calendar year month date day hour minute second this module provides other functions including time stamp from 1 1024 second to year alarm wakeup timer time update interruption and 32 768 kHz output Time stamp function can record maximum of 8 events Using the backup battery char...

Page 7: ...ncy selection 32 768 kHz 1024 Hz 1 Hz When output is stopped the FOUT pin is High impedance INT Open Drain Output This pin is used to output alarm signals timer signals time update signals and other signals This pin is an N ch open drain VDD Power supply pin Possible to supply different voltage from VIO VIO Interface power supply pin Input to supply the voltage same as a host VOUT Internal voltage...

Page 8: ... VDD are different VDD VBAT VIO 1 8 V 3 3 V R 0 1 F Re chargeable Battery EDLC or 0 1 F 1 0 F VOUT Figure 3 Connection example 1 Ex 2 VIO and VDD are the same VDD VBAT VIO 3 3 V 3 3 V R 0 1 F Re Chargeable battery EDLC or 1 0 F VOUT Figure 4 Connection example 2 Ex 3 Connecting a Non RE Chargeable battery VDD VBAT VIO VDD R 0 1 F Non Re chargeable battery 1 0 F VOUT Figure 5 Connection example3 Ex...

Page 9: ...RX8111CE Page 5 ETM61E 01 Ex 5 Connecting a Non Re Chargeable battery VDD VBAT VIO VDD R Non Re Chargeable Battery 0 1 F VOUT SW1 SW2 SW3 INIEN 0 CHGEN 0 SESEL1 0 01b Figure 7 Connection example 5 ...

Page 10: ...ax 0 7 0 3 0 62 0 42 0 2 Min 0 4 0 35 0 7 0 4 0 9 1 1 0 3 3 2 0 2 Typ 3 24 2 5 0 2 Typ 2 54 Figure 8 External dimensions 5 2 Marking Layout RX8111CE 1 Pin Mark Logo Production lot R8111A 123B Frequency Tolerance A A B None Type Contents displayed indicate the general markings and display but are not the standards for the fonts sizes and positioning Figure 9 Marking Layout ...

Page 11: ...rface supply voltage VIO VDD 1 6 V 5 5 V 1 6 3 0 5 5 V Clock supply voltage VCLK Supply from VBAT VVLF 3 0 5 5 V VLF detection voltage VVLF VOUT low detection Voltage 1 1 V Operating temperature Ta No condensation 40 25 85 C VCLK Min is available by initializing in VDD VDET1 When first Power ON for internal initializing VDD must be more than 1 45V VDET1 8 Frequency Characteristics Table 4 Frequenc...

Page 12: ... V High Input voltage VIH SCL SDA 0 8 VIO 5 5 V EVIN 0 8 VOUT VOUT 0 3 V Low Input voltage VIL SCL SDA GND 0 3 0 2 VIO V EVIN GND 0 3 0 2 VOUT High Output voltage VOH1 FOUT VIO 5 0 V IOH 1 mA 4 5 5 0 V VOH2 VIO 3 0 V IOH 1 mA 2 2 3 0 VOH3 VIO 3 0 V IOH 100 A 2 9 3 0 Low output voltage VOL1 FOUT VIO 5 0 V IOL 1 mA GND GND 0 5 V VOL2 VIO 3 0 V IOL 1 mA GND GND 0 8 VOL3 VIO 3 0 V IOL 100 A GND GND 0 ...

Page 13: ...Chargeable current characteristics of VBAT VDD 5 5V Figure 12 Circuit of charge to re chargeable Battery 9 1 3 Reference Value Of Switching Element Table 6 Reference value of switching element Item Characteristics Condition Current tolerance 40 mA Max SW1 SW2 SW3 ON 25 C Diode Vf 0 60 V 1 mA Typ 0 85 V 10 mA Typ VDD 3 0 V 25 C Diode IR 50 nA Max VR 5 5 V 40 C to 85 C Charge current from VBAT must ...

Page 14: ...H 4 0 0 6 s Rise time for SCL and SDA tr 1 0 0 3 s Fall time for SCL and SDA tf 0 3 0 3 s Allowable spike time on bus tSP 50 50 ns Timing Chart tHD DAT tSU DAT tHD STA tLOW tHIGH 1 fSCL tr tf tSU STA SDA SCL START CONDITION S BIT 7 MSB A7 BIT 6 A6 ACK A Protocol tBUF tSU STO STOP CONDITION P START CONDITION S P A tHD STA tSU STA S BIT 0 LSB R W S tSP Figure 13 I2 C Timing Chart I2 C interface is r...

Page 15: ...wer on reset occurs on rising edge of VOUT voltage Note During first Power ON for internal initialization VDD must be over 1 45 V VDET1 VMain GND VDD tR1 tF tR2 VDET1 Back up operation tCL tCD tCU VDET1 VDET1 I2 C Communication Communication Access denied VDD VCLK_Min GND VOUT tR1 GND VBAT VBAT 1 Figure 14 Power on Sequence Table 9 Power up down characteristics Item Symbol Condition Min Typ Max Un...

Page 16: ...le 3 Access is prohibited within 40 ms the supply voltage exceeds min VCLK Clock supply voltage VDD 1 6 V VDD VDD detect voltage VDET1 Internal oscillation Illustration tSTA Oscillation start time 0 3 s Typ Access is enabled Normal operation start Minimum voltage of keeping time and date VCLK During power on initialization or power supply voltage recovery after drop in clock maintenance voltage 40...

Page 17: ... if VLF is 1 it available after step5 4 2ms is time for RESET processing Note Except using this RESET sequence don t access to D0h from D3h and never write 1 to a TEST bit 11 Reference information 11 1 Reference Data 1 Example of frequency and temperature characteristics 150 100 50 0 50 0 50 100 Temperature C Frequency f T 10 6 T 25 C Typ 0 035 10 6 Typ Finding the frequency stability 1 Frequency ...

Page 18: ...rthermore please input the VDD or GND most recent voltage as much as possible 4 Handling of unused pins Disposal of unused input terminals When an input terminal is open state it causes increase of a consumption electric current and the behavior that are instability Please fix an unused input terminal to the voltage that is near to VDD or GND 2 Notes on packaging 1 Soldering heat resistance If the...

Page 19: ... events for alarm settings such as date day hour and minute settings When an interrupt event occurs the AF bit value is set to 1 and the INT pin goes to low level to indicate that an event has occurred 4 Lower Operation Voltage Detection Function VLF Lower voltage of VOUT terminal can be detected During power on initialization or recovery of backup this function judges the clock data reliability I...

Page 20: ...p HOUR z z 20 10 8 4 2 1 25h Time Stamp WEEK z 6 5 4 3 2 1 0 26h Time Stamp DAY z z 20 10 8 4 2 1 27h Time Stamp MONTH z z z 10 8 4 2 1 28h Time Stamp YEAR 80 40 20 10 8 4 2 1 29h Status Stamp z z VLOW VCMP VDET z XST z 2Ah No Function z z z z z z z z 2Bh EVIN Setting EHL ET1 ET0 PDN PU1 PU0 OVW 2Ch SEC Alarm AE 40 20 10 8 4 2 1 2Dh Timer Control z z z z TBKON TBKE TMPIN TSTP 2Eh Time Stamp contro...

Page 21: ...e Stamp HOUR 20 10 8 4 2 1 4C 5C 6C 7C Time Stamp DAY 20 10 8 4 2 1 4D 5D 6D 7D Time Stamp MONTH 10 8 4 2 1 4E 5E 6E 7E Time Stamp YEAR 80 40 20 10 8 4 2 1 4F 5F 6F 7F Status stamp VLOW VCMP VDET XST After the initial power up from 0 V or in case the VLF bit returns 1 make sure to initialize all registers before using the RTC The TEST bit 3Fh bit7 is used by the manufacturer for testing Be sure to...

Page 22: ...ounter 1 X X X X X X X X 1Ch Timer Counter 2 X X X X X X X X 1Dh Extension Register 0 0 0 0 0 0 1 0 1Eh Flag Register 1 0 0 0 0 0 1 X 1Fh Control Register 0 0 0 0 0 0 0 0 Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 20h Time Stamp 1 1024S 0 0 0 0 X X X X 21h Time Stamp 1 256S X X X X X X X X 22h Time Stamp SEC 0 X X X X X X X 23h Time Stamp MIN 0 X X X X X X X 24h Time Stamp HO...

Page 23: ... 3 bit 2 bit 1 bit 0 40 50 60 70 Time Stamp 1 256S X X X X X X X X 41 51 61 71 Time Stamp SEC X X X X X X X X 42 52 62 72 Time Stamp MIN X X X X X X X X 43 53 63 73 Time Stamp HOUR X X X X X X X X 44 54 64 74 Time Stamp WEEK X X X X X X X X 45 55 65 75 Time Stamp DAY X X X X X X X X 46 56 66 76 Time Stamp Year X X X X X X X X 47 57 67 77 Status Stamp X X X X X X X X 48 58 68 78 Time stamp 1 256S X...

Page 24: ...the wake up timer interrupt function If customer does not use this function TE TIE TSTP TMPIN should be 0 0 0 0 TSEL1 TSEL0 1 0 TF do not care Please refer to 14 2 Wake up timer interrupt function for the details 4 WADA AF AIE bit These bits are used to control operation of the alarm interrupt function If customer does not use this function WADA should be 1 AIE 0 AF do not care Please refer to 14 ...

Page 25: ...e details 1 Time Stamp Status recording register 20h 29h 40h 7Fh In case of event occasion time stamp 1 1024 sec Yea and inner status are recorded into these registers 2 EVIN terminal control register 2Bh Setting of EVIN terminal 3 Command Trigger Time Stamp Control register 2Eh 2Fh It is used for time stamp trigger timing via I2 C bus 4 Time Stamp Trigger Control Register 35h It is used for time ...

Page 26: ...0 0 0 1 0 16h YEAR 1 0 0 0 1 0 0 0 Note With caution that writing non existent time data may interfere with normal operation of the clock counter Note Time starts at the moment of STOP bit operation H L timing 14 1 1 Clock Counter 1 SEC MIN register These registers are 60 base BCD counters When update signals were generated from a lower counter a upper counter is one incremented At the timing when...

Page 27: ... 0 0 1 0 0 04 h Wednesday 0 0 0 0 1 0 0 0 08 h Thursday 0 0 0 1 0 0 0 0 10 h Friday 0 0 1 0 0 0 0 0 20 h Saturday 0 1 0 0 0 0 0 0 40 h 14 1 3 Calendar Counter 1 DAY MONTH register The DAY register is a variable between 28 base and 31 base BCD counter that is influenced by the month and the leap year The MONTH register is a 12 base BCD counter triggered by carry over of the day register Table 15 DA...

Page 28: ...0 to the TE and TIE bits 1 Down counter for wake up interrupt timer Timer Counter 2 1 0 This register is used to set the default preset value for the counter Any count value from 1 000001h to 16777216 FFFFFFh can be set Be sure to write 0 to the TE bit before writing the preset value When TE 0 read out data of timer counter is default Preset value And when TE 1 read out data of timer counter is ju...

Page 29: ... Timer Flag TF Data Description Write 0 The TF bit is cleared to zero to prepare for the next status detection Clearing this bit to zero is not enable the INT low output status to be cleared to Hi Z 1 Invalid writing 1 will be ignored Read 0 1 Wake up timer interrupt events are detected Result is retained until this bit is cleared to zero 5 TIE bit Timer Interrupt Enable This bit is used to contro...

Page 30: ... up timer interrupt 1 Normal FOUT port 8 TSTP bit Timer Stop This bit is used to stop wake up timer count down Table 23 TSTP bit Timer Stop TE STOP TBKE TSTP Description 1 0 0 0 Writing a 0 to this bit cancels stop status restarts timer counts down The reopening value of the countdown is a stopping value 1 Count stops 1 X Setting of TSTP value becomes invalid and the count does not stop even if se...

Page 31: ...6 Source clock 4096 Hz TSEL1 0 0 0 64 Hz TSEL1 0 0 1 1 Hz TSEL1 0 1 0 1 60 Hz TSEL1 0 1 0 0 1 244 14 s 15 625 ms 1 s 1 min 410 100 10 ms 6 406 s 410 s 410 min 3840 0 9375 s 60 000 s 3840 s 3840 min 4096 1 0000 s 64 000 s 4096 s 4096 min 16777216 1 13 h 72 81 h 4660 h 31 9 Year 14 2 4 Diagram of wake up timer interrupt function Figure 20 Wake up timer block diagram TMPIN bit TIE bit F O U T FOUT IN...

Page 32: ...on of wake up timer Internal operation Write operation Wake up timer start Wake up timer stops TF bit 0 makes INT clear before tRTN period Figure 21 Wake up timer timing chart After wake up counter interrupt pre set data is re loaded to counter Count down repeats from pre set value By setting TE 0 1 wake up counter starts counting down Pre set value count down is available by setting TE 0 1 only ...

Page 33: ... alarm Day alarm register Reg 19h the setting selected via the WADA bit determines whether WEEK alarm data or DAY alarm data will be set If WEEK has been selected via the WADA bit multiple days can be set such as Monday Wednesday Friday Saturday Unwanted alarm term is decided by setting respective AE bit 1 If AE is set to 1 this alarm term becomes inactive Ex WEEK Alarm DAY Alarm 19h 80h AE 1 hour...

Page 34: ...cified and WADA bit 0 Table 29 WEEK alarm example 1 Week is specified WADA bit 0 bit 7 AE bit 6 S bit 5 F bit 4 T bit 3 W bit 2 T bit 1 M bit 0 S HOUR Alarm MIN Alarm SEC Alarm Monday through Friday at 7 00 AM 1 minute 60 sec alarm 0 0 1 1 1 1 1 0 07 h 00h AE bit 1 Every Saturday and Sunday for 30 minutes each hour Hour value is ignored 0 1 0 0 0 0 0 1 AE bit 1 30 h 00h Every day at 6 59 30 AM 0 1...

Page 35: ... output AF bit Event occurs 1 0 Hi Z L 1 0 Internal operation 内部動作 Write operation Figure 23 Alarm interrupt timing chart AF Clear to 0 Internal second carry DAY detection result WEEK detection result WEEK DAY AE HOUR detection result HOUR AE MIN detection result MIN AE SEC detection result SEC AE WADA INT AIE AF Flag 1 0 ...

Page 36: ...e User can set INT output inactive 1 USEL bit Update Interrupt Select This bit is used to select second update or minute update as the timing for generation of time update interrupt events Table 32 USEL bit Update Interrupt Select USEL data Description Write Read 0 Selects second update once per second as the timing for generation of interrupt events 1 Selects minute update once per minute as the ...

Page 37: ...put UF bit Carry tRTN period period period period 1 0 Hi Z L 1 0 Clearing UF bit 0 does not change INT status Internal Operation Write Operation Clearing UIE bit 0 makes INT Hi Z before tRTN period Figure 25 Time Update timing chart I N T Carry Sec UF Flag tRTN Carry Min UF clears to Zero USEL bit Update Control Circuit F64Hz UIE bit ...

Page 38: ... POR or XST Table 37 VLF bit Voltage Low Flag VLF Data Description Write 0 The VLF is cleared to 0 and waiting for next low voltage detection 1 Invalid writing 1 will be ignored Read 0 Oscillation status is normal RTC register data are valid 1 Either power on reset or X tal oscillation stop is detected The result remains until clearing 0 User can check the RTC status and initialize by software At ...

Page 39: ...n output becomes Hi Z 14 6 1 FOUT control register Table 42 FOUT control register Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1Dh Extension Register FSEL1 FSEL0 USEL TE WADA ETS TSEL1 TSEL0 FOUT pin can be terminated as wake up timer too When FOUT function is needed TMPIN should be 0 and INT pin should be wake up timer interrupt output 14 6 2 FOUT function table 1 FSEL1 FSEL0 ...

Page 40: ...Figure 26 Battery Backup switchover function block diagram 14 7 2 Battery backup switchover related register Table 44 Battery backup switchover related register Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 32h Power Switch Control CHGEN INIEN z z SWSEL1 SWSEL0 SMPT1 SMPT0 1 CHGEN bit Charge Enable SW VBAT pin VOUT pin automatic control Table 45 CHGEN bit Charge Enable CHGEN Dat...

Page 41: ...ntrol Initial power on Please refer 4 Connection Example Figure6 and Figure7 Figure 27 Battery Backup Switchover Control Initial power on 5 Non re chargeable battery control INIEN 1 CHGEN 0 Figure 28 Battery Backup Switchover Control non rechargeable battery ...

Page 42: ...nytime with setting SW1 VDD VOUT ON OFF intermittently These two bits control SW1 OFF period and user can check much precision voltage by preventing reverse current from VBAT to VDD when main VDD shuts down VDD voltage low detection VDET1 is active anytime so lower voltage detection moves RTC into backup mode immediately regardless SW1 OFF time These SW1 OFF occur every second Table 47 SMPT bit Sa...

Page 43: ...RX8111CE Page 39 ETM61E 01 Figure 30 VDD detection VDET1 SW1 intermittent operation ...

Page 44: ...N OFF OFF OFF 1 1 1 Prohibited Other than 1 1 Automatic control ON 9 Voltage detection intermittent timing Table 49 Voltage detection timing Power Supply Normal mode Backup mode VDD drive CHGEN 1 INIEN 1 VDD drive CHGEN 0 INIEN 1 VDD drive CHGEN 0 INIEN 0 VBATdrive VDD detection VDET1 anytime anytime suspended Once a 31 25 ms VDD vs VBAT VCMP Twice a 3 0 s suspended suspended Suspended VBAT detect...

Page 45: ...stamp record time 1 128 sec SEC MIN HOUR DAY MONTH YEAR Status Stamp Figure 31 Time Stamp function 14 8 2 Time Stamp related register Table 50 Time Stamp function register Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1Dh Extension Register FSEL1 FSEL0 USEL TE WADA ETS TSEL1 TSEL0 1Eh Flag Register POR z UF TF AF EVF VLF XST 1Fh Control Register z z UIE TIE AIE EIE z STOP 2Bh EV...

Page 46: ...ent Flag This register is be set to 1 when event occurs Table 52 EVF bit Event Flag EVF Data Description Write 0 In case INT L output it is set to Hi Z 1 Invalid writing 1 will be ignored Read 0 1 EVIN input is detected The result remains until clearing to 0 3 EIE bit Event Interrupt Enable This register control INT interrupt output at the moment of the event EVF 0 1 Table 53 EIE bit Event Interru...

Page 47: ...32 EVIN chattering prevention function 6 PDN PU1 PU0 bit Pull Down Select Pull Up Select These registers controls EVIN pin input internal Pull up Pull down resistor value Pull up resistor is connected to VOUT Pull down resistor to GND Table 56 PDN PU register Pull Down Select Pull Up Select Condition PDN PU1 RU0 Resistor value status No connection 0 0 0 Hi Z Pull up 0 0 1 500 k 0 1 0 1 M 0 1 1 10 ...

Page 48: ...ime stamp trigger by I2 C Bus ON RTC timer counter and internal status data are recorded into 20h 29h by I2 C reading access from 2Fh The read data of 2Fh is 00h Also multi access is available 2 Time stamp access timing Time stamp processing is done at ACK operation just after slave address sending of command trigger reading R 0 1 0 INTpin SDA Master SCL Time stamp trigger 0 SDA Slave ACK Trigger ...

Page 49: ... stored register Address Function Time stamp record 20h Time Stamp 1 1024Sec 256 Hz 512 Hz 21h Time Stamp 1 256Sec 1 Hz 128 Hz 22h Time Stamp Sec sec 23h Time Stamp Min min 24h Time Stamp Hour hour 25h Time Stamp Week week 26h Time Stamp Day day 27h Time Stamp Month month 28h Time Stamp Year year 29h Status Stamp RTC internal status Table 60 Status Stamp Address Function bit 7 bit 6 bit 5 bit 4 bi...

Page 50: ...p at the moment of event Table 64 XST bit Time Stamp X tal Oscillation Stop XST Data Description Read 0 Normal Internal Crystal oscillation 1 Internal Crystal oscillation stops 14 8 6 RTC internal event triggered time stamp multiple times stamp In addition to EVIN pin input triggered the RTC time stamp can be triggered by internal event Also time stamp events are continuously recoded into RAM up t...

Page 51: ...ore the result data Also if user used fixed SW combination don t use this register Refer to Figure 38 Table 67 EVDET bit Enable VDET EVDET Data Description Write 0 No time stamp event even VDET1 is detected 1 When RTC moves to backup mode time stamp event occurs 3 EVLOW bit Enable VLOW This bit controls VLOW detection ON OFF and time stamp VLOW ON OFF A common register for VLOW function and time s...

Page 52: ...e User can modify directly RAM data via I2 C if necessary 2 TSCLR bit Time Stamp Clear The operation of writing 1 to this bit makes address 36h clear to initialize and this bit be reset to 0 automatically Time stamp function should be disenabled by resetting ETS to 0 before this operation Time stamp clear Table 71 TSCLR bit Time Stamp Clear TSCLR Data Description Write 0 Invalid writing 0 will be ...

Page 53: ...p Empty This bit is monitor bit of RAM empty Table 74 TSEMP bit Time Stamp Empty TSEMP Data Description Read 0 There is some data recording in the RAM area 40h 7fh 1 There is no data recording in the RAM area 40h 7fh 3 TSAD2 TSAD1 TSAD0bit Time Stamp Address This bits are monitor register of the latest time stamp RAM address Table 75 TSDA bit Time Stamp Address TSAD TSAD2 TSAD1 TSAD0 Address point...

Page 54: ...ach of system 1 Power on initializing example After internal oscillation start VLF can be cleared to 0 Start Wait At least 40 ms wait time is needed So that it is stable RTC 40 ms is not oscillation startup time When RTC returned from battery backup normally VLF is 0 and after initial power On VLF is 1 When VLF is 1 recommended initializing all register data VLF 1 YES YES NO VLF 0 clear Wait VLF 0...

Page 55: ...Setup Alarm Setup Alarm function Setup Wake up timer function Setup Wakeup Timer function Reg 1Dh Setup Timer function Clear self monitoring Bits Reg 32h Setup of battery backup switchover function Setup interruption output Reg 1Eh Reg 1Eh Reg 10h 16h Figure 39 Example flow Initialization EX1 ...

Page 56: ... of initialization initialize all data STOP 0 Resetting STOP bit to 0 and clock starts The clock starts just after resetting to 0 If user does not use STOP bit operation be aware that clock start just after writing second data Also if user write second year at once I2 C bus acknowledge reset second and less than second counters and clock starts Be aware that battery backup switchover function is i...

Page 57: ...l for working time counter of machine etc Wake up timer setting Clear TE bit to 0 to inactivate wake up timer interruption Set TSEL1 TSEL0 bit combination to count down period source clock Clear the TF bit by zero Reg 1D h Reg 1E h Figure 43 Example flow Setting wake up timer interrupt function 7 Setting Alarm Example Next Processing Reg 1F h Set AIE bit to 1 for outputs Alarm interruption from IN...

Page 58: ...tivate time stamp interrupt function An event makes INT pin interruption output Set ETS bit to 1 to activate time stamp function Reg 1F h Reg 1D h Waiting event YES NO Reg 2B h Setup EVIN pin input pull up pull down resistor combination Reg 1D h Clear ETS bit by 0 to inactivate time stamp function Reg 1E h Clear EVF bit by 0 Reg 1D h Reset ETS bit to 0 to inactivate time stamp function The reason ...

Page 59: ...g 35h bit3 0 0000b Time Stamp Control 2 bit3 0 0 To inactive RTC internal status detection time stamp Read Reg 2Fh Reading 2Fh makes time stamp triggering and data 1 1024 sec is stored to 20h Read Reg 20h Reading 1 1024 sec data from 20h Reed Reg 21h Reading 1 128 sec data from 21h Next processing Write Reg 2Eh bit0 1b COMTG 1 To activate Command Trigger Write Reg 2Eh bit0 0b COMTG 0 To inactivate...

Page 60: ...t3 0 0 To inactive RTC internal status detection time stamp Read Reg 2Fh Read Reg 20h Reed Reg 21 28h Reading 21h 28h data Write Reg 2Eh bit0 0b COMTG 1 To activate Command Trigger Reading 2Fh makes time stamp triggering and data 1 1024 sec is stored to 20h Reading 1 1024 sec data from 20h COMTG 0 To inactivate Command Trigger Write Reg 1Dh bit2 0b Write Reg 35h bit3 0 0000b Write Reg 2Eh bit0 1b ...

Page 61: ...topping I2 C Bus communications SCL START condition SDA 0 95 s Max Repeated START RESTART condition STOP condition S Sr P Figure 48 I2 C Bus start stop timing START condition repeated START condition and STOP condition 1 START condition The SDA level changes from high to low while SCL is at high level 2 STOP condition This condition regulates how communications on the I2 C Bus are terminated The S...

Page 62: ...llector ports in order to enable AND connections to multiple devices SCL and SDA are both connected to the VIO line via a pull up resistance Consequently SCL and SDA are both held at high level when the Bus is released when communication is not being performed Master Transmitter Receiver Slave Transmitter Receiver Other I2C bus device CPU etc RX8111CE SDA SCL VIO Master Transmitter Receiver Slave ...

Page 63: ... 4 CPU transfers address for reading from RX8111CE 5 Check for ACK signal from RX8111CE 6 CPU transfers RESTART condition Sr in which case CPU does not transfer a STOP condition P 7 CPU transfers RX8111CE s slave address with the R W bit set to read mode 8 Check for ACK signal from RX8111CE from this point on the CPU is the receiver and the RX8111CE is the transmitter 9 Data from address specified...

Page 64: ...RX8111CE Page 60 ETM61E 01 15 Circuit Diagram Connection ...

Page 65: ...upt register 32 Table 32 USEL bit Update Interrupt Select 32 Table 33 UF bit Update Flag 32 Table 34 UIE bit Update Interrupt Enable 32 Table 35 RTC Internal status detection registers 34 Table 36 POR bit Power On Reset 34 Table 37 VLF bit Voltage Low Flag 34 Table 38 XST bit X tal Oscillation Stop 34 Table 39 EVIN bit EVIN Level 34 Table 40 VCMP bit VCMP 35 Table 41 VLOW bit VLOW 35 Table 42 FOUT...

Page 66: ...k diagram 31 Figure 23 Alarm interrupt timing chart 31 Figure 24 Time Update Interrupt block diagram 33 Figure 25 Time Update timing chart 33 Figure 26 Battery Backup switchover function block diagram 36 Figure 27 Battery Backup Switchover Control Initial power on 37 Figure 28 Battery Backup Switchover Control non rechargeable battery 37 Figure 29 Battery Backup Switchover Control rechargeable bat...

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