RX
−
8564
LC
Page
−
21
ETM12E-01
3) Down counter for fixed-cycle timer
(
Timer Register
)
This register is used to set the default (preset) value for the counter. Any count value from 1
(01
h)
to
255
(FFh)
can be set
When the fixed-cycle timer interrupt function is operating, the down counter counts down one step per
source clock cycle, and when the count value goes from 01h to 00h, an event such as changing the TF bit
value to "1"
occurs.
∗
When the fixed-cycle timer function has been stopped (when the TE bit value has been changed from "1"
to "0"), the timer's down counter value and preset value both become invalid.
∗
The preset value must be written again (when TE = "0") in order to start the fixed-cycle timer interrupt
function again.
∗
The status during a countdown can be checked by reading this register.
(
However, since the read data is not held (the data may be changing), to obtain accurate data the
countdown status should be read twice and then compared.
)
4) TE bit
(
Timer Enable
)
This bit enables operation of the of the fixed-cycle timer interrupt function to start.
TE
Data
Description
0
Stops fixed-cycle timer interrupt function
Write / Read
1
Starts fixed-cycle timer interrupt function
5) TF bit
(
Timer Flag
)
This is a flag bit that retains the result when a fixed-cycle timer interrupt event is detected.
If it was already cleared to zero, this value changes from "0" to "1" when an event occurs, and the new
value is retained.
TF
Data
Description
0
The TF bit is cleared to zero (to cancel the interrupt event), to prepare for the
next event detection.
Note)
Even after the interrupt event has been canceled, the fixed-cycle timer
function operates continuously as long as the TE bit
(Timer Enable)
value
is "1".
∗
Level interrupt mode
(single-shot operation)
1)
Clearing the TF bit to zero cancels the low-level status of the /INT pin
(the /INT pin goes to Hi-Z status)
.
2)
When the TE bit value remains "1", the timer's down counter continues
to count down, and when the counter value goes form 01h to 00h, the
TF bit value is again changed to "1", the /INT pin goes to low level, and
an event occurs.
Write
1
This bit is invalid after a "1" has been written to it.
0
Fixed-cycle timer interrupt events are not detected.
Read
1
Fixed-cycle timer interrupt events are detected.
∗
Result is retained until this bit is cleared to zero
