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EPSON
E0C6006 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
<Input interrupt programming related precautions>
Port K input
Factor flag set Not set
Mask register
Active status
➀
When the content of the mask register is rewritten, while the port K input is
in the active status. The input interrupt factor flag is set at
➀
.
Fig. 4.10.1.3 Input interrupt timing
When using an input interrupt, if you rewrite the content of the mask register, when the value of the
input terminal which becomes the interrupt input is in the active status (input terminal = low status),
the factor flag for input interrupt may be set.
For example, a factor flag is set with the timing of
➀
shown in Figure 4.10.1.3. However, when clear-
ing the content of the mask register with the input terminal kept in the low status and then setting it,
the factor flag of the input interrupt is again set at the timing that has been set.
Consequently, when the input terminal is in the active status (low status), do not rewrite the mask
register (clearing, then setting the mask register), so that a factor flag will only set at the falling edge
in this case. When clearing, then setting the mask register, set the mask register, when the input
terminal is not in the active status (high status).
4.10.2 Interrupt mask register
One interrupt mask register is available to each interrupt factor flag to mask an interrupt request. Data
can be written to or read from the mask register. An interrupt request is enabled with "1" set in the
register, and masked with "0" set in the register. At initial reset, the mask register is reset to "0".
Table 4.10.2.1 Interrupt mask register
Interrupt mask register
ETI2
ETI8
ETI32
EIREM
EIK1
EIK0
(0F3H•D2)
(0F3H•D1)
(0F3H•D0)
(0F2H•D2)
(0F2H•D1)
(0F2H•D0)
Interrupt factor flag
TI2
TI8
TI32
IREM
IK1
IK0
(0F1H•D2)
(0F1H•D1)
(0F1H•D0)
(0F0H•D2)
(0F0H•D1)
(0F0H•D0)
4.10.3 Interrupt vector
In response to an interrupt request, the CPU starts interrupt processing. The CPU saves the PC into the
stack and makes a jump to the interrupt address, that is the interrupt handling routine. The interrupt
address is indirectly specified by an interrupt factor. Interrupt addresses are assigned to page 1, steps 01H
to 0FH of the PC. In other words, the low-order 4 bits of the PC are indirectly addressed by interrupt
factors, as follows:
Table 4.10.3.1 Interrupt vector
PC
PCS3
PCS2
PCS1
PCS0
Interrupt factor
Timer interrupt requested
Timer interrupt not requested
REM interrupt requested
REM interrupt not requested
K10–K13 interrupt requested
K10–K13 interrupt not requested
K00–K03 interrupt requested
K00–K03 interrupt not requested
Value
1
0
1
0
1
0
1
0
Examples:
• Only timer interrupt requested
— Jump to page 1, step 08H
• Both timer interrupt and REM interrupt requested
— Jump to page 1, step 0CH