Epson DLQ-3000+, Service Manual

Page: 79 / 262

Operating Principles
Rev. A
2-17
2.3.1 Interface Circuit
This section gives information on the parallel/serial interfaces of the DLQ-3000+.
Bi-directional parallel interface
The gate array E05B46 manages the IEEE-1284 nibble mode function using the internal
IFU (Interface Unit). It latches data from the host computer by the /STB signal and
automatically sends the BUSY signal. When the data is stored in the buffer, the gate
array clears the BUSY and sends /ACK back to the host computer.
Serial interface
Received data RXD sent from the host computer (i.e. , which is also
applied to an optional interface.) is transferred to the CPU via the transceiver IC, and then
to the input buffer. The CPU directly outputs TXD data (
!
). The codes
DC1/DC2 and DC3 are outputs when the input buffer is full, and DC1 is output when the
buffer memory recovers to the normal level. The signal REV (same as
" #
$
) is output to the port PC0 of the CPU to control the DTR. The printer resumes
printing when the CR code is received or the input buffer is full.
Type-B interface
Type-B interface is also controlled by the gate array E05B46.
P A R A L E L L D A T A
( D 0 - 7 )
R E V D T R R X T T X D
D T R R X T T X D
B U S Y
P E
L H
S T B
I N I T
A F X T
A C K
E R R
I N H
S L C T
A D D R E S S / D A T A
R D
H W R
C E
R E S E T
R E A D Y
W R R D Y
C M R E Q
R D R E Q
S y s t e m B u s
G a t e A r r a y
E 0 5 B 4 6
C P U
A D D R E S S / D A T A
T r a n s c e i v e r I C
M A X 2 0 2
P A R A L E L L I / F
T y p e - B I / F
S E R I A L I / F
Figure 2-12. Interface Circuit Block Diagram