EPOX M762A Series, Installation Manual

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Award BIOS Setup
Idle Cycle Limit:
This bit field controls the number of idle cycles to wait before precharging
an idle bank. Idle cycles are defined as cycles in which no valid requests
are asserted.
The choice: 0, 8, 12, 16, 24, 32, 48 and Disabled.
Page Hit Limit:
This bit field controls the number of consecutive page hit requests to allow
before choosing a non-PH request.
The choice: 1, 4, 8 and 16.
Trc Cycle:
This bit field indicates the Trc timing value (bank cycle time: minimum time
from activate to activate of same bank).
The choice: 3, 4, 5, 6, 7, 8, 9 and 10.
Trp Cycle:
This bit field indicates the Trp timing value (precharge time: time from
precharge to activate on the same bank).
The choice: 1, 2, 3 and 4.
Tras Cycle:
This bit field indicates the Tras timing value (minimum bank active time:
time from activate to precharge of same bank).
The choice: 2, 3, 4, 5, 6, 7, 8 and 9.
CAS Latency Time:
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing.
The choice: 2, 3.
Trcd Cycle:
This bit field indicates the Trcd timing value (RAS to CAS latency, delay
from active to RD/WR command).
The choice: 1, 2, 3 and 4.
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